Multiple frequency digital phase locked loop

Claim 1

An improved multiple frequency digital phase locked loop (DPLL) for processing received data signal and producing an output signal which is phase-locked to the received data signal, comprising: (a) phase comparator means having first and second inputs, wherein the first input is coupled to the received data signal and the second input is coupled to the DPLL output signal, and an output for providing an output signal indicative of the relative phase between said incoming data signal and said DPLL output signal; (b) clock means for generating a reference clock signal; (c) programmable divider means, coupled to said reference clock signal and having an output and programmable inputs, for generating a programmable clock signal related to said reference clock signal according to a divider ratio controlled by said programmable inputs; (d) digital means, coupled to the output of said programmable divider means for generating first and second derived clock signals, one such signal being in a delayed relation to the other; (e) phase and frequency adjust means coupled to said clock means for producing a composite clock signal by selectively adding or subtracting said first and second derived clock signals, periodically, at a rate defined by said programmable clock signal to effect a frequency adjustment or by individually adding or subtracting pulses in response to said phase comparator output signal to effect a phase adjustment; (f) frequency divider means coupled to said phase and frequency adjust means for processing said composite clock signal to produce the digital phase-locked loop output signal.