US4110557A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase lock oscillator for use in data processing system
Assignee: Unisys Corp
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Filing: 1976-12-27
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Granted: 1978-08-29
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Expires: 1996-12-27
Abstract
Abstract A phase lock oscillator system employing a phase and frequency detector which receives the data pulses and the clocking signal modulated to include only the clocking pulses corresponding in timed sequence to the actual data pulses for generating an error signal to regulate the voltage controlled oscillator.
Inventors
- 👤 W. Donald Huber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:50
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
105 words
A system for generating clocking signal responsive in phase and frequency to a data signal having intermittent pulses indicating data, said system comprising: an oscillator for providing a clocking signal responsive in frequency and phase to an error signal; a phase and frequency detector for receiving and comparing the data signal pulses to said clocking signal for generating an error signal for regulating the oscillator so the phase and frequency of the clocking signal equals that of the data signal; and means to prevent the transmission of the clocking signal to the phase and frequency detector when no data pulse exists in the data signal.
Claim 2
Independent Claim
105 words
A system for generating clocking signal responsive in phase and frequency to a data signal having intermittent pulses indicating data, said system comprising: an oscillator for providing a clocking signal responsive in frequency and phase to an error signal; a phase and frequency detector for receiving and comparing the data signal pulses to said clocking signal for generating an error signal for regulating the oscillator so the phase and frequency of the clocking signal equals that of the data signal; and means to prevent the transmission of the clocking signal to the phase and frequency detector when no data pulse exists in the data signal.
Claim 3
Dependent Claim
48 words
A system for generating a clocking signal as defined in claim 1 wherein said means to prevent the transmission of the clocking signal includes a demodulator receiving said data signal, in combination with means for generating a signal responsive to the occurrence of pulses in the data signal.
Claim 4
Dependent Claim
53 words
A system for generating a clocking signal as defined in claim 2 including a frequency divider connected to receive the clocking signal from the oscillator and divide said clocking signal responsive to the signal responsive to the occurrence of data pulses before transmission of the clocking signal to the phase and frequency detector.
Claim 5
Dependent Claim
41 words
A system for generating a clocking signal as defined in claim 3 including means to delay transmission of the data signal to the phase and frequency detector to synchronize the data signal with the clocking signal received from the frequency divider.
Claim 6
Dependent Claim
40 words
A system for generating a clocking signal as defined in claim 4 including means for generating a gain control signal responsive to the data signal, and means to regulate the gain of the system responsive to the gain control signal.
Claim 7
Independent Claim
135 words
A system for generating a clocking signal responsive in phase and frequency to a data signal having intermittent pulses indicating data, said system comprising in combination: a voltage controlled oscillator for providing a clocking signal responsive in phase and frequency to an error signal; a frequency divider for receiving and dividing said clocking signal responsive to a frequency control signal; a shift register receiving said data signal; circuit means for transmitting said clocking signal to the shift register sequencing said register; means to generate said frequency control signal for regulating said frequency divider responsive to the occurrence of data signal pulses in the shift register; and a phase and frequency detector receiving said divided clocking signal from the frequency divider and the data signal for generating the error signal for regulating the voltage controlled oscillator.
Claim 8
Independent Claim
135 words
A system for generating a clocking signal responsive in phase and frequency to a data signal having intermittent pulses indicating data, said system comprising in combination: a voltage controlled oscillator for providing a clocking signal responsive in phase and frequency to an error signal; a frequency divider for receiving and dividing said clocking signal responsive to a frequency control signal; a shift register receiving said data signal; circuit means for transmitting said clocking signal to the shift register sequencing said register; means to generate said frequency control signal for regulating said frequency divider responsive to the occurrence of data signal pulses in the shift register; and a phase and frequency detector receiving said divided clocking signal from the frequency divider and the data signal for generating the error signal for regulating the voltage controlled oscillator.
Claim 9
Dependent Claim
48 words
A system for generating a clocking signal as defined in claim 6 including means to delay transmission of the data signal to the phase and frequency detector to synchronize the arrival of the data signal in the detector with the divided clocking signal received from the frequency divider.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |