US3878334A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data synchronizing systems
Assignee: General Dynamics Corp
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Filing: 1974-04-10
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Granted: 1975-04-15
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Expires: 1994-04-10
Abstract
Abstract A bit synchronizer system is disclosed which is adaptive to varying input conditions such as noise and jitter of data signals particularly PCM telemetry signals. The signal to noise parameter of the input data signal is obtained from a matched filter having a response matched to signals which are orthogonal to the input data signal. This matched filter also detects transitions in the input data signal which are used to lock a phse locked loop. The loop generates a local clock which is synchronous with the incoming data and can be applied to detect the incoming data bits and reconstruct them into noise and jitter-free output data. Control signals are also extracted from the loop which represent the jitter (viz., the rate of change of the phase) of the input signal. The bandwidth of the loop is varied in accordance with the jitter and noise to signal parameters to the optimum bandwidth for the prevailing noise to signal ratio and jitter on the incoming data signal.
Inventors
- 👤 Peter H Halpern
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:49
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H03; H03L; H03L7/00; H03L7/06; H03L7/08
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
256 words
A system for acquisition of data transmitted in the form of repetitive input data signals having successive signalling intervals of equal duration during which data signals representing different data can be transmitted, changes in the state of said data being represented by transitions in said data signals, said system comprising a. a filter matched to signals which are orthogonal to said data signals, said data signals being applied to said filter, b. first circuit means connected to said filter for providing a first error signal having an amplitude which is a measure of the noise to signal characteristic of said data signal, c. a phase locked loop having a phase detector which provides an error voltage to control the phase of output signals produced by a voltage controlled oscillator, which is coupled to said phase detector, and also having means in said loop for controlling the bandwidth thereof, d. means connected to said filter and being coupled to said phase detector for detecting said transitions and locking said loop in response thereto, e. means coupled to said loop for providing a second error signal having an amplitude which is a measure of the rms variations in frequency of said output signal, f. means for applying said first and second error signals to said bandwidth control means for adapting said loop for changes in the noise in said data signals and error in the frequency of said signalling intervals thereof, and g. means for detecting the data represented by said data signals synchronously with said output signals.
Claim 2
Independent Claim
256 words
A system for acquisition of data transmitted in the form of repetitive input data signals having successive signalling intervals of equal duration during which data signals representing different data can be transmitted, changes in the state of said data being represented by transitions in said data signals, said system comprising a. a filter matched to signals which are orthogonal to said data signals, said data signals being applied to said filter, b. first circuit means connected to said filter for providing a first error signal having an amplitude which is a measure of the noise to signal characteristic of said data signal, c. a phase locked loop having a phase detector which provides an error voltage to control the phase of output signals produced by a voltage controlled oscillator, which is coupled to said phase detector, and also having means in said loop for controlling the bandwidth thereof, d. means connected to said filter and being coupled to said phase detector for detecting said transitions and locking said loop in response thereto, e. means coupled to said loop for providing a second error signal having an amplitude which is a measure of the rms variations in frequency of said output signal, f. means for applying said first and second error signals to said bandwidth control means for adapting said loop for changes in the noise in said data signals and error in the frequency of said signalling intervals thereof, and g. means for detecting the data represented by said data signals synchronously with said output signals.
Claim 3
Independent Claim
158 words
A system for producing output signals synchronously with periodic input signals having transitions which occur at intervals related to the period of said input signals, said system comprising a. means including a phase locked loop for generating said output signals, b. means responsive to said input signals for providing a fist output corresponding to the noise to signal ratio of said input signals and a second output corresponding to said transitions, c. means coupled to said loop for generating a third output corresponding to the variations in frequency of said loop output signals, d. means responsive to said second output for phase locking said loop to said transitions, and e. means responsive to said first and third outputs for varying the bandwidth of said loop inversely with said noise to signal ratio and directly with said frequency variations so as to adapt said loop to independently accommodate for conditioNs of noise and frequency filter in said input signal.
Claim 4
Independent Claim
158 words
A system for producing output signals synchronously with periodic input signals having transitions which occur at intervals related to the period of said input signals, said system comprising a. means including a phase locked loop for generating said output signals, b. means responsive to said input signals for providing a fist output corresponding to the noise to signal ratio of said input signals and a second output corresponding to said transitions, c. means coupled to said loop for generating a third output corresponding to the variations in frequency of said loop output signals, d. means responsive to said second output for phase locking said loop to said transitions, and e. means responsive to said first and third outputs for varying the bandwidth of said loop inversely with said noise to signal ratio and directly with said frequency variations so as to adapt said loop to independently accommodate for conditioNs of noise and frequency filter in said input signal.
Claim 5
Dependent Claim
30 words
The invention as set forth in claim 2 wherein said input signal responsive means includes a matched filter means having a response matched to signals orthogonal to said input signals.
Claim 6
Dependent Claim
49 words
The invention as set forth in claim 3 wherein said input signals are data signals coded in accordance with one of the NRZ and split phase codes, and said filter response is matched to data signals coded in accordance with the other of said NRZ and split phase codes.
Claim 7
Dependent Claim
28 words
The invention as set forth in claim 2 wherein said input signal responsive means includes circuit means for providing a maximum amplitude output signal coincident with said transitions.
Claim 8
Dependent Claim
67 words
The invention as set forth in claim 3 wherein said matched filter means includes a first network having said response matched to signals orthogonal to said input signals and a second network having a response matched to said input signals, means connected to said first and to said second network for providing said first output, and means connected to said first network for providing said second output.
Claim 9
Dependent Claim
91 words
The invention as set forth in claim 6 wherein said means connected to said first and second network which provides said first output includes first square law average circuit means connected to said first network and second square law average circuit means connected to said second network, and means for dividing 6 times the difference between said second and first square law average circuit outputs by the difference between four times said second square law average circuit output and said first square law average circuit outputs to provide said first output.
Claim 10
Dependent Claim
90 words
The invention as set forth in claim 3 wherein said input signal responsive means further comprises, detector means responsive to said matched filter output for providing a signal which is a function of the level of said input signal and the noise accompanying said input signal, clipping circuit means for providing another signal which is principally a function of the level of said input signal alone, and means for dividing the difference between said detector means and clipping means signals by said clipping means signal to provide said first output.
Claim 11
Dependent Claim
83 words
The invention as set forth in claim 8 wherein said phase locked loop includes a phase detector which provides said loop locking means, said bandwidth varying means, a voltage controlled oscillator, and means for applying said output signal to said phase detector; said input signal responsive means responsive to said second output includes peak detector means for generating signals occurring at the peaks of matched filter output; and means for applying said last named signals to said phase detector as said second output.
Claim 12
Dependent Claim
85 words
The invention as set forth in claim 8 wherein said phase locked loop includes a phase detector which receives said second output and provides said loop locking means, said bandwidth varying means, a voltge controlled oscillator for generating said output signal, and means for applying said oscillator signal also to said phase detector, and wherein said means coupled to said loop for generating said third output includes means for detecting variations in the amplitude of voltage which controls said oscillator for providing said third output.
Claim 13
Dependent Claim
47 words
The invention as set forth in claim 10 wherein said amplitude variations detecting means includes circuit means for providing an output which varies with the square of the amplitude of the input thereto, means for a.c. coupling said oscillator control voltage to said last named circuit means.
Claim 14
Dependent Claim
55 words
The invention as set forth in claim 10, wherein said bandwidth varying means includes means for multiplying said first output and said third output with one of said first and third outputs being the inverse of the other, and means for controlling the gain of said loop as a function of said multiplying means output.
Claim 15
Dependent Claim
72 words
The invention as set forth in claim 10 wherein said bandwiDth varying means includes a variable bandwidth filter having a resistor which determines the bandwidth thereof, said resistor havine resistance which is dependent upon the intensity of illumination thereof, a source of illumination for said resistor and means for varying the intensity of said source directly as a function of said first output and inversely as a function of said third output.
Claim 16
Dependent Claim
86 words
The invention as set forth in claim 6 wherein said phase locked loop includes a phase detector which provides said loop locking means, said bandwidth varying means, a voltage controlled oscillator, and means for applying said output signal to said phase detector; said input signal responsive means responsive to said second output includes peak detector means for generating signals occurring at the peaks of matched filter output; and means for applying said signals from said peak detector means to said phase detector as said second output.
Claim 17
Dependent Claim
86 words
The invention as set forth in claim 6 wherein said phase locked loop includes a phase detector which receives said second output and provides said loop locking means, said bandwidth varying means, a voltage controlled oscillator for generating said output signal, and means for applying said oscillator signal also to said phase detector, and wherein said means coupled to said loop for generating said third output includes means for detecting variations in the amplitude of the voltage which controls said oscillator for providing said third output.
Claim 18
Dependent Claim
46 words
The invention as set forth in claim 15 wherein said amplitude variations detecting means includes circuit means for providing an output which varies the square of the amplitude of the input thereto, means for a.c. coupling said oscillator control voltage to said last named circuit means.
Claim 19
Dependent Claim
55 words
The invention as set forth in claim 15, wherein said bandwidth varying means includes means for multiplying said first output and said third output with one of said first and third outputs being the inverse of the other, and means for controlling the gain of said loop as a function of said multiplying means output.
Claim 20
Dependent Claim
72 words
The invention as set forth in claim 15 wherein said bandwidth varying means includes a variable bandwidth filter having a resistor which determines the bandwidth thereof, said resistor having resistance which is dependent upon the intensity of illumination thereof, a source of illumination for said resistor and means for varying the intensity of said source directly as a function of said first output and inversely as a function of said third output.
Claim 21
Dependent Claim
93 words
The invention as set forth in claim 3 wherein said phase locked loop comprises a phase detector which provides said loop locking means, said bandwidth control means, a voltage controlled oscillator which provides said output signal and means for applying said output signal to said phase detector, and wherein means are provided also responsive to said second output for detecting variations in the frequency thereof and generating an error signal corresponding to said frequency variations, and means in said loop for applying said frequency error signal to control the frequency of said oscillator.
Claim 22
Dependent Claim
48 words
The invention as set forth in claim 19 wherein said applying means for said frequency error signal comprises a summing circuit in said loop to which said phase detector output and said frequency error signal are applied, said summing circuit being output connected to said bandwidth control means.
Claim 23
Dependent Claim
41 words
The invention as set forth in claim 3 further comprising means coupled to the input of said matched filter and responsive to said matched filter output for controlling the amplitude of said input signal at the input of said matched filter.
Claim 24
Dependent Claim
80 words
The invention as set forth in claim 21 wherein said amplitude control means comprises a variable gain amplifier for applying said input signal to said matched filter input, and means responsive to the average value of the difference between portions of said matched filter output which exceed a first scalar level and portions of said matched filter output which exceed a second scalar level greater than said first level for generating a signal for controlling the gain of said amplifier.
Claim 25
Dependent Claim
96 words
The invention as set forth in claim 22 wherein said matched filter includes a first network having said response matched to signals orthogonal to said input signals and a second network having a response matched to said input signals, said first network providing said matched filter output means responsive to said first network output for providing said input signal responsive means first and second outputs, and means responsive to said second matched filter network output and to said second output for controlling the d.c. offset of the input signals at the input of said matched filter.
Claim 26
Dependent Claim
61 words
The invention as set forth in claim 23 wherein said d.c. offset control means includes a drift control circuit connected between said variable gain amplifier and said matched filter input, and means for sampling said second network output during the interval of said second output and providing a signal corresponding to the average value thereof for controlling said drift control circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-14 | 1978-10-14 | 1979-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-14 | 1982-10-14 | 1983-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-14 | 1986-10-14 | 1987-04-15 | $7700.00 | Window Closed / Lapsed |