Methods for making neighboring wells for VLS1 CMOS components

Claim 1

In an improved method for the manufacture of neighboring wells implanted with dopant ions differing in conductivity type in the manufacture of VLSI complementary MOS field effect transistors (CMOS) circuits, wherein n + -doped, or, alternatively, p + -doped, silicon having an n - -doped, or, alternatively, p - -doped, epitaxial layer situated thereon is employed as a semiconductor substrate into which first p-wells are introduced upon employment of a composite layer consisting of a silicon oxide layer and a silicon nitride layer which composite layer is covered with a first photoresist as masking layer for n-wells, and then said n-wells are introduced upon employment of a silicon oxide layer covered with a second photoresist as masking layer for said p-wells, and whereby the edge of said composite layer is shifted in the direction of said n-wells by means of directed, lateral under-etching of said composite layer and by means of subsequent oxidation preceding the production of said n-wells, the improvement comprising: conducting said under-etching of said composite layer by isotropically etching into said silicon nitride mask layer under said first photoresist layer with all layers lying therebelow being not appreciably etched; and generating an auxiliary polysilicon layer immediately above said silicon nitride mask layer and structured together with said first photoresist layer to protect said silicon nitride mask layer during said under-etching.