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US4630356A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming recessed oxide isolation with reduced steepness of the birds' neck

Assignee: International Business Machines Corp
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Filing: 1985-09-19
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Granted: 1986-12-23
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Expires: 2005-09-19
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Abstract

Abstract Disclosed is a method of forming in a monocrystalline silicon body an optimum recessed oxide isolation structure with reduced steepness of the bird's neck. Starting from a monocrystalline silicon body, there is formed thereon a layered structure of first silicon dioxide, polycrystalline silicon, second silicon dioxide and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form the oxide isolation pattern within the silicon body. The exposed areas of the silicon body are anisotropically reactive ion etched to an initial portion of the desired depth obtaining the corresponding portion of the trench having substantially vertical walls. Then by chemical etching the trench is extended to a final portion of the desired depth obtaining inwardly sloped walls in the final portion. The body is then thermally oxidized until the desired oxide isolation penetrates to the desired depth within the silicon body.

Inventors

  • 👤 Rosemary Christie
  • 👤 Bao-Tai Hwang
  • 👤 San-Mei Ku
  • 👤 Janet M. Sickler

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 00:12
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/13; H10P; H10P50/00; H10P50/69; H10P50/691; H10P50/692; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0124

Claims Analysis

Total Claims: 20
Claim 1
Independent Claim 150 words
Method of forming a recessed oxide isolation with reduced steepness of the bird's neck in a silicon substrate comprising: providing a semiconductor silicon substrate; forming on said substrate surface a mask stack of first silicon dioxide layer, polycrystalline silicon layer, second silicon dioxide layer and silicon nitride layer in that order; patterning said mask stack to form openings at the areas where it is desired to form an oxide isolation pattern within said semiconductor substrate; anisotropically reactive ion etching the silicon substrate exposed by the openings in said stack to a first portion of the desired depth obtaining therein trenches having substantially vertical walls; chemically etching said silicon substrate to extend the trenches to a second portion of the desired depth and obtain inwardly sloped walls in the second portion; and thermally oxidizing the exposed silicon in said trenches to form said isolation with reduced steepness of the bird's neck.
Claim 2
Dependent Claim 150 words
Method of forming a recessed oxide isolation with reduced steepness of the bird's neck in a silicon substrate comprising: providing a semiconductor silicon substrate; forming on said substrate surface a mask stack of first silicon dioxide layer, polycrystalline silicon layer, second silicon dioxide layer and silicon nitride layer in that order; patterning said mask stack to form openings at the areas where it is desired to form an oxide isolation pattern within said semiconductor substrate; anisotropically reactive ion etching the silicon substrate exposed by the openings in said stack to a first portion of the desired depth obtaining therein trenches having substantially vertical walls; chemically etching said silicon substrate to extend the trenches to a second portion of the desired depth and obtain inwardly sloped walls in the second portion; and thermally oxidizing the exposed silicon in said trenches to form said isolation with reduced steepness of the bird's neck.
Claim 3
Dependent Claim 17 words
The process as recited in claim 1 wherein said patterning is achieved by anisotropic reactive ion etching.
Claim 4
Dependent Claim 21 words
The process as recited in claim 1 wherein said first silicon dioxide layer is grown by thermal oxidation of said substrate.
Claim 5
Dependent Claim 23 words
The process as recited in claim 1 wherein said second silicon dioxide layer is obtained by thermal oxidation of said polycrystalline silicon layer.
Claim 6
Dependent Claim 23 words
The process as recited in claim 1 wherein said depth of said first portion is about 50% to 75% of said desired depth.
Claim 7
Dependent Claim 23 words
The process as recited in claim 1 wherein the slope of said inwardly sloped walls is about 45° with respect to the vertical.
Claim 8
Dependent Claim 16 words
The process as recited in claim 1 further comprising removing said mask stack by chemically etching.
Claim 9
Dependent Claim 21 words
The process as recited in claim 1 wherein said first silicon dioxide layer thickness is between about 5 to 10 nm.
Claim 10
Dependent Claim 19 words
The process as recited in claim 1 wherein said second silicon dioxide layer thickness is between about 3-7 nm.
Claim 11
Dependent Claim 19 words
The process as recited in claim 1 wherein the thickness of said polycrystalline silicon is between about 30-80 nm.
Claim 12
Dependent Claim 19 words
The process as recited in claim 1 wherein the thickness of the silicon nitride is between about 30-70 nm.
Claim 13
Dependent Claim 16 words
The process as recited in claim 7 wherein said polycrystalline silicon is removed by using pyrocatechol.
Claim 14
Dependent Claim 123 words
Method for manufacturing a monolithic integrated circuit structure comprising: providing a monocrystalline silicon body; forming on said silicon body a mask stack of first silicon dioxide, polycrystalline silicon, second silicon dioxide and silicon nitride layers, in that order; anisotropically reactive ion etching through said mask stack in the area of said silicon body where it is desired to form an oxide isolation pattern within said body; continuing said etching into said silicon body to a portion of the desired depth; chemically etching said silicon body to the said desired depth whereby the sides of the trench in said silicon body are sloped; and thermally oxidizing the exposed silicon in said trench to form recessed oxide isolation with reduced steepness of the bird's neck.
Claim 15
Dependent Claim 123 words
Method for manufacturing a monolithic integrated circuit structure comprising: providing a monocrystalline silicon body; forming on said silicon body a mask stack of first silicon dioxide, polycrystalline silicon, second silicon dioxide and silicon nitride layers, in that order; anisotropically reactive ion etching through said mask stack in the area of said silicon body where it is desired to form an oxide isolation pattern within said body; continuing said etching into said silicon body to a portion of the desired depth; chemically etching said silicon body to the said desired depth whereby the sides of the trench in said silicon body are sloped; and thermally oxidizing the exposed silicon in said trench to form recessed oxide isolation with reduced steepness of the bird's neck.
Claim 16
Dependent Claim 15 words
The process as in claim 13 wherein the sides of said trench are sloped inward.
Claim 17
Dependent Claim 22 words
The process as in claim 13 wherein said second silicon dioxide layer is relatively thin compared to said first silicon dioxide layer.
Claim 18
Dependent Claim 49 words
The process as in claim 13 further comprising the following said thermal oxidation step, the steps of: removing said silicon nitride by using hot phosphoric acid; chemically removing said second silicon dioxide layer by using buffered hydrofluoric acid; and chemically removing said polycrystalline silicon layer by using pyrocatechol solution.
Claim 19
Dependent Claim 26 words
The process as in claim 14 wherein the angle of inclination with the vertical of said sloped sides is in the range of approximately 40-50 degrees.
Claim 20
Dependent Claim 18 words
The process as in claim 17 wherein said portion is about 50% to 70% of said desired depth.

References Cited (Backward Citations)

US3970486A Cited
US3534234A Cited
US3900350A Cited
US4104086A Cited
US4170500A Cited
US4272308A Cited
EP0071203A2 Cited
US4508757A Cited
US4516316A Cited
JPS6160851A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-12-22 1990-06-23 1990-12-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-12-22 1994-06-23 1994-12-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-12-22 1998-06-23 1998-12-23 $7700.00 Window Closed / Lapsed

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