US4525378A
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Method for manufacturing VLSI complementary MOS field effect circuits
Assignee: Siemens AG
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Filing: 1984-06-05
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Granted: 1985-06-25
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Expires: 2004-06-05
Abstract
Abstract A method for manufacturing VLSI complementary MOS field effect transistor circuits (CMOS circuits). By use of a suitable gate material, preferably a gate material comprised of silicides of high melting point metals, a threshold voltage of n-channel and p-channel CMOS-FETs having gate oxide thicknesses d GOX in a range of 10 to 30 nm is simultaneously symmetrically set by means of a single channel ion implantation. Given employment of tantalum silicide, the gate oxide thickness d GOX is set to 20 nm and the channel implantation is executed with a boron dosage of 3×10 11 cm -2 and an energy of 25 keV. In addition to achieving a high low-level break down voltage for short channel lengths, this enables the elimination of a photolithographic mask. This represents an improvement with respect to yield and costs. The method serves for the manufacture of analog and digital CMOS circuits in VLSI technology.
Inventors
- 👤 Ulrich Schwabe
- 👤 Erwin P. Jacobs
- 👤 Franz Neppl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:15
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/667; H10D64/668; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
195 words
A method for manufacturing VLSI complementary MOS field effect transistor circuits (CMOS circuits) wherein p-doped or n-doped tubs are generated in a semiconductor substrate for acceptance of the n-channel and p-channel transistors of the circuits, corresponding dopant atoms for setting various transistor threshold voltages being introduced into the tubs by ion implantation, a masking being provided for the individual ion implantations, and a manufacture of the source, drain, and gate regions as well as a generation of an intermediate and insulating oxide and of an interconnect level being provided, wherein the improvement comprises the steps of: (a) employing a gate material having a work function φ M higher than n + -polysilicon gate material, the work function φ M being matched to a thickness of a gate oxide thickness d GOX ; (b) setting the gate oxide thickness d GOX to values in a range from 10 to 30 nm; and (c) executing a single, common channel ion implantation for p-channel and n-channel transistors, said channel ion implantation being matched such that, with a given gate oxide thickness d GOX , threshold voltages of n-channel and p-channel transistors are symmetrical and have a given value.
Claim 2
Independent Claim
195 words
A method for manufacturing VLSI complementary MOS field effect transistor circuits (CMOS circuits) wherein p-doped or n-doped tubs are generated in a semiconductor substrate for acceptance of the n-channel and p-channel transistors of the circuits, corresponding dopant atoms for setting various transistor threshold voltages being introduced into the tubs by ion implantation, a masking being provided for the individual ion implantations, and a manufacture of the source, drain, and gate regions as well as a generation of an intermediate and insulating oxide and of an interconnect level being provided, wherein the improvement comprises the steps of: (a) employing a gate material having a work function φ M higher than n + -polysilicon gate material, the work function φ M being matched to a thickness of a gate oxide thickness d GOX ; (b) setting the gate oxide thickness d GOX to values in a range from 10 to 30 nm; and (c) executing a single, common channel ion implantation for p-channel and n-channel transistors, said channel ion implantation being matched such that, with a given gate oxide thickness d GOX , threshold voltages of n-channel and p-channel transistors are symmetrical and have a given value.
Claim 3
Dependent Claim
16 words
A method according to claim 1 wherein the gate material comprises a high melting point metal.
Claim 4
Dependent Claim
14 words
A method according to claim 1 wherein the gate material comprises a metal silicide.
Claim 5
Dependent Claim
25 words
A method according to claim 1 wherein silicides of metals selected from the group tantalum, titanium, molybdenum and tungsten are employed as said gate material.
Claim 6
Dependent Claim
348 words
A method for manufacturing a CMOS circuit according to claim 1, including the steps of using n-doped silicon base material as the bases and tantalum silicide as the gate material; and: (a) manufacturing the p-tub with a boron ion implantation in the n-doped substrate covered with an oxide layer after masking remaining regions with a silicon nitride mask; (b) executing a local oxidation process and in-diffusion of boron ions; (c) stripping the silicon nitride masking; (d) manufacturing the n-tub with a phosphorous ion implantation and subsequent in-diffusion of phosphorous ions; (e) executing a field implantation for the n-channel transistors in the region of the p-tub after masking of the n-tub by means of a silicon nitride and photoresist layer, and masking an entire transistor region of the n-channel transistor in the p-tub with a silicon nitride layer; (f) manufacturing field oxide regions by means of local oxidation by use of a silicon nitride layer as a masking; (g) providing a thermal oxidation of the entire surface after stripping of the silicon nitride masking up to a gate oxide thickness d GOX of approximately 20 nm; (h) providing a surface-wide boron ion implantation for doping of the n-channel and of the p-channel with a dosage of 1 to 4×10 11 cm -2 and an energy of 5-60 keV; (i) depositing and structuring tantalum silicide for formation of the gate regions; (j) providing a surface-wide deposition of an oxide layer in such a thickness that the later source/drain implantations of the n-channel and p-channel transistors are not masked; (k) executing a photoresist technique whereby all regions except the p-tub regions remain covered with photoresist; (l) executing a phosphorous ion implantation for production of the source/drain regions of the n-channel transistors and stripping of the photoresist structures; (m) executing a further photoresist technique whereby all regions except the n-tub regions remain covered with photoresist; (n) executing a boron ion implantation for production of the source/drain regions of the p-channel transistors and stripping of the photoresist structures; and (o) providing the insulating layer, the contact hole regions, and the metal interconnect structure.
Claim 7
Dependent Claim
40 words
A method according to claim 5 including the step of employing as a substrate n-doped silicon oriented in a (100)-direction and having an epitaxial layer on an n + -doped silicon substrate having a conductivity of 0.01 through 0.02 Ωcm.
Claim 8
Dependent Claim
60 words
A method according to claim 5 including the step of executing the boron ion implantation according to method step (a) with a dosage of 1.5×10 12 cm -2 and an energy of 160 keV, and executing the phorphorous ion implantation according to method step (e) with a dosage of approximately 7×10 11 cm -2 and an energy of 160 keV.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-24 | 1988-12-24 | 1989-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-24 | 1992-12-24 | 1993-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-24 | 1996-12-24 | 1997-06-25 | $7700.00 | Window Closed / Lapsed |