US4799992A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlevel dielectric fabrication process
Assignee: Texas Instruments Inc
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Filing: 1985-10-31
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Granted: 1989-01-24
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Expires: 2005-10-31
Abstract
Abstract A process for the fabrication of integrated circuits, wherein the interlevel dielectric material is partially etched back prior to reflow. This provides a pre-reflow profile which prevents filament problems in subsequently-patterned conductor levels, and which also avoids cracking of the interlevel dielectric during reflow.
Inventors
- 👤 Kalipatnam V. Rao
- 👤 Allan T. Mitchell
- 👤 James L. Paterson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
81 words
A process for fabricating integrated circuits, comprising the steps of: providing a partially fabricated integrated circuit having a first patterned conductor layer thereupon; depositing an interlevel dielectric overall; anisotropicaly etching said interlevel dielectric to reduce its minimum thickness by at least 10 percent; opening contact holes in said interlevel dielectric at a plurality of predetermined locations after said anisotropically etching step; reflowing said interlevel dielectric, after said anisotropically etching step; and forming a second patterned conductor layer in a predetermined pattern.
Claim 2
Dependent Claim
81 words
A process for fabricating integrated circuits, comprising the steps of: providing a partially fabricated integrated circuit having a first patterned conductor layer thereupon; depositing an interlevel dielectric overall; anisotropicaly etching said interlevel dielectric to reduce its minimum thickness by at least 10 percent; opening contact holes in said interlevel dielectric at a plurality of predetermined locations after said anisotropically etching step; reflowing said interlevel dielectric, after said anisotropically etching step; and forming a second patterned conductor layer in a predetermined pattern.
Claim 3
Dependent Claim
17 words
The process of claim 1, wherein said reflowing step is after said step of opening contact holes.
Claim 4
Dependent Claim
17 words
The process of claim 1, wherein said reflowing step is after said step of opening contact holes.
Claim 5
Dependent Claim
18 words
The process of claim 1 wherein said step of depositing said interlevel dielectric overall comprises substantially conformal deposition.
Claim 6
Dependent Claim
24 words
The process of claim 1, wherein said step of anisotropically etching said interlevel dielectric reduces its minimum thickness by no more than 50 percent.
Claim 7
Dependent Claim
21 words
The process of claim 1, further comprising the additional step of densifying said interlevel dielectric prior to said anisotropically etching step.
Claim 8
Dependent Claim
13 words
The process of claim 1, wherein said interlevel dielectric comprises a silicate glass.
Claim 9
Dependent Claim
13 words
The process of claim 1, wherein said interlevel dielectric comprises a borophosphosilicate glass.
Claim 10
Dependent Claim
12 words
The process of claim 1, wherein said interlevel dielectric comprises a polymer.
Claim 11
Dependent Claim
21 words
The process of claim 1, wherein said step of anisotropically etching said interlevel dielectric has an anisotropy of at least 10:1.
Claim 12
Dependent Claim
17 words
The process of claim 1, wherein said step of anisotropically etching said interlevel dielectric comprises plasma etching.
Claim 13
Dependent Claim
26 words
The process of claim 1, wherein said first patterned conductor layer comprises two thin-film conductors separated by a dielectric and patterned to have mutually coincident sidewalls.
Claim 14
Dependent Claim
29 words
The process of claim 1, wherein said first patterned conductor layer comprises a polycrystalline material which is more than 30% silicon, and said second conductor layer comprises a metal.
Claim 15
Dependent Claim
14 words
The process of claim 1, wherein said first patterned conductor layer comprises a metal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-24 | 1992-07-25 | 1993-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-24 | 1996-07-25 | 1997-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-24 | 2000-07-25 | 2001-01-24 | $7700.00 | Window Closed / Lapsed |