GAAS FET logic having increased noise margin

Claim 2

A multiple input logic gate for implementing the NOR function comprising: an input stage including a plurality of enhancement mode FETs, said enhancement mode FETs having gate terminals for receiving logical input signals and a common source terminal, said input stage further including a depletion mode FET which is capable of level shifting the voltage present at said common source terminal, and an inverter stage connected to said depletion mode FET, said depletion mode FET being coupled between said common source terminal and an input of said inverter stage.

Claim 3

The gate of claim 1 wherein said inverter stage is electrically connected to a push-pull stage comprising two enhancement mode FETs.

Claim 4

The gate of claim 2 wherein said push-pull stage is connected to an additional depletion mode FET.

Claim 5

The gate of claim 1 wherein said input stage is formed from GaAs enhancement mode MESFETs, said depletion mode FET is a GaAs MESFET, and said inverter stage comprises one enhancement mode GaAs MESFET and one depletion mode GaAs MESFET.

Claim 6

A logic gate capable of being implemented using GaAs enhancement mode and depletion mode MESFETs comprising: a source follower input stage comprising at least one enhancement mode FET having a drain terminal connected to a power supply, a gate terminal for receiving an input signal and a source terminal whose voltage is responsive to said input signal, said input stage further including a depletion mode FET capable of level shifting the voltage at said source terminal, and an inverter stage connected to said depletion mode FET and comprising an enhancement mode driver FET and a depletion mode load FET.

Claim 7

A logic gate capable of being implemented using GaAs enhancement mode and depletion mode MESFETs comprising: a source follower input stage comprising at least one enhancement mode FET having a drain terminal connected to a power supply, a gate terminal for receiving an input signal and a source terminal whose voltage is responsive to said input signal, said input stage further including a depletion mode FET capable of level shifting the voltage at said source terminal, and an inverter stage connected to said depletion mode FET and comprising an enhancement mode driver FET and a depletion mode load FET.

Claim 8

A logic gate capable of being implemented using GaAs enhancement mode and depletion mode MESFETs comprising a source following input stage comprising at least a first enhancement mode FET having a gate terminal for receiving a logic input signal, a drain terminal connected to a voltage supply, and a source terminal for producing a voltage signal responsive to said logic input signal, and a first depletion mode FET having a drain terminal connected to the source terminal of said first enhancement mode FET and a source terminal connected to a gate terminal, said first depletion mode FET being capable of level shifting said voltage produced at said source terminal of said first enhancement mode FET, and an inverter stage comprising a second enhancement mode FET and a second depletion mode FET, a gate terminal of said second enhancement mode FET being connected to the source terminal of said level shifting first depletion mode FET.

Claim 9

A logic gate capable of being implemented using GaAs enhancement mode and depletion mode MESFETs comprising a source following input stage comprising at least a first enhancement mode FET having a gate terminal for receiving a logic input signal, a drain terminal connected to a voltage supply, and a source terminal for producing a voltage signal responsive to said logic input signal, and a first depletion mode FET having a drain terminal connected to the source terminal of said first enhancement mode FET and a source terminal connected to a gate terminal, said first depletion mode FET being capable of level shifting said voltage produced at said source terminal of said first enhancement mode FET, and an inverter stage comprising a second enhancement mode FET and a second depletion mode FET, a gate terminal of said second enhancement mode FET being connected to the source terminal of said level shifting first depletion mode FET.

Claim 10

The logic gate of claim 6 wherein said gate further includes current supply means connected to the gate terminal of the second enhancement mode FET for discharging the gate terminal of said second enhancement mode FET.

Claim 11

The logic gate of claim 7 wherein said current supply means comprises a third depletion mode FET.

Claim 12

A logic gate comprising: at least one stage for performing the AND function including a depletion mode FET having gate, drain and source terminals, said drain terminal being capable of connection to a voltage supply and said gate terminal being connected to said source terminal, and a plurality of diodes, each diode having an anode and a cathode, each of said anodes being connected to said source terminal and each of said cathodes being capable of receiving a logic input signal, a stage for performing the OR function including at least one enhancement mode FET having a gate terminal connected to said source terminal of said depletion mode FET in said AND stage and a source terminal, and a diode which is capable of level shifting the voltage present at said source terminal of said enhancement mode FET, and an inverter stage connected to said diode.

Claim 13

A logic gate comprising: at least one stage for performing the AND function including a depletion mode FET having gate, drain and source terminals, said drain terminal being capable of connection to a voltage supply and said gate terminal being connected to said source terminal, and a plurality of diodes, each diode having an anode and a cathode, each of said anodes being connected to said source terminal and each of said cathodes being capable of receiving a logic input signal, a stage for performing the OR function including at least one enhancement mode FET having a gate terminal connected to said source terminal of said depletion mode FET in said AND stage and a source terminal, and a diode which is capable of level shifting the voltage present at said source terminal of said enhancement mode FET, and an inverter stage connected to said diode.

Claim 14

The gate of claim 9 wherein said FETs are GaAs MESFETS and said diodes are Schottky barrier diodes.

Claim 15

A GaAs solid stage circuit comprising, first and second interconnected logic gates capable of performing distinct Boolean functions, said first gate including a level shifting Schottky barrier diode, said second gate including a level shifting depletion mode MESFET dimensioned for providing said second gate with a noise margin that substantially matches the noise margin of said first gate.

Claim 16

A GaAs solid stage circuit comprising, first and second interconnected logic gates capable of performing distinct Boolean functions, said first gate including a level shifting Schottky barrier diode, said second gate including a level shifting depletion mode MESFET dimensioned for providing said second gate with a noise margin that substantially matches the noise margin of said first gate.

Claim 17

The circuit of claim 11 wherein said first gate is capable of performing the AND-OR-INVERT function and said second gate is capable of performing the NOR function.