Electrically erasable fused programmable logic array

Claim 2

A programmable logic array comprising: a plurality of logic input means for receiving a plurality of input logic signals; a plurality of logic gates, each gate having a plurality of inputs; a plurality of electrically alterable programmable fuse means, each having an input and an output electrically isolated from the output of any other electrically alterable programmable fuse means and each being programmable into a first state in which said electrically alterable programmable fuse means operates and functions as a logic inverter or into a second state in which said electrically alterable programmable fuse means provides at its output a preselected logic signal; means for coupling each input of said plurality of inputs of each logic gate to a selected output of said electricaly alterable programmable fuse means, each input of each logic gate being connected to a different programmable fuse means output than any other logic gate input for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output, whereby said input means are selectively logically coupled to selected ones of said logic gates; and programming means for selectively programming said fuse means.

Claim 3

A programmable logic array as set out in claim 1 wherein said electrically alterable programmable fuse means comprises an electrically erasable transistor and one or more transistors coupled to said electrically erasable transistor.

Claim 4

A programmable logic array as set out in claim 1 wherein said programming means comprises: programming signal control means for providing a programming signal to selected ones of said electrically alterable programmable fuse means; and erase signal control means for supplying an erase signal to selected ones of said electrically alterable programmable fuse means.

Claim 5

A programmable logic array as set out in claim 1 wherein said logic gates and said electrically alterable programmable fuse means are implemented in a CMOS integrated circuit.

Claim 6

The combination as claimed in claim 1 wherein said plurality of electrically alterable programmable fuse means is arranged in a matrix array having rows and columns; one row of fuse means for each one of said logic gates, with the outputs of the fuse means of each row being connected to the inputs of the same logic gate.

Claim 7

The combination as claimed in claim 5 further including a primary control line per column, a logic line per column, and a secondary control line per row of said fuse means.

Claim 8

A programmable logic array comprising: a plurality of logic array input means for receiving a plurality of input logic signals; a plurality of logic gates, each gate having a plurality of inputs; a plurality of fuse means, each fuse means having an output independent of, and not directly connected to, the output of any other fuse means and each input of each logic gate being selectively connected to a different fuse means output than any other logic gate input whereby the output of each fuse means is connected to only one input of said logic gates for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output, each fuse means having programmable logic states, for alterably coupling selected ones of said input means to selected ones of said logic gate inputs by performing the NAND logic operation on the input logic signals received by said fuse means from said selected ones of said input means and the programmed logic state of said fuse means and providing the logic output of said NAND operation to said selected ones of said logic gates; and programming means for programming selected ones of said fuse means.

Claim 9

A programmable logic array comprising: a plurality of logic array input means for receiving a plurality of input logic signals; a plurality of logic gates, each gate having a plurality of inputs; a plurality of fuse means, each fuse means having an output independent of, and not directly connected to, the output of any other fuse means and each input of each logic gate being selectively connected to a different fuse means output than any other logic gate input whereby the output of each fuse means is connected to only one input of said logic gates for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output, each fuse means having programmable logic states, for alterably coupling selected ones of said input means to selected ones of said logic gate inputs by performing the NAND logic operation on the input logic signals received by said fuse means from said selected ones of said input means and the programmed logic state of said fuse means and providing the logic output of said NAND operation to said selected ones of said logic gates; and programming means for programming selected ones of said fuse means.

Claim 10

A programmable logic array as set out in claim 7 wherein said programmable fuse means comprises an electrically erasable transistor and one or more transistors coupled to said electrically erasable transistor.

Claim 11

A programmable logic array as set out in claim 8 wherein said electrically erasable transistor opeates in a D.C. mode having approximately constant load characteristics during normal logic operations of said logic array when said fuse means is programmed in a first one of said two programming states.

Claim 12

A programmable logic gate array as set out in claim 7 wherein said programming means comprises: programming signal control means for providing a programming signal to selected ones of said fuse means; and erase signal control means for supplying an erase signal to selected ones of said fuse means.

Claim 13

A programmable logic array as set out in claim 7 wherein said fuse means and said logic gates are implemented in a CMOS integrated circuit.

Claim 14

A CMOS integrated circuit programmable logic array comprising: a plurality of inputs for receiving a plurality of input logic signals; a plurality of logic gates each logic gate having a plurality of inputs; a plurality of electrically erasable fuse means each having an output independent of, and not directly connected to, the output of any other electrically erasable fuse means, and the inputs of each logic gate being connected to the outputs of a selected number of electrically erasable fuse means, each logic gate being connected to a different number of electrically erasable fuse means than any other logic gate, for selectively logically coupling selected ones of said inputs to selected ones of said logic gates and for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output; a plurality of program signal control means coupled to selected ones of said logic gates and selected ones of said fuse means, for selectively supplying a programming signal to said selected ones of said fuse means; and a plurality of erase signal control means coupled to selected ones of said fuse means and selected ones of said inputs, for selectively supplying erase signals to said selected ones of said fuse means; wherein said fuse means is selectively programmed into one of two programming states by selective application of predetermined level signals to said inputs, said program signal control means, and said erase signal control means.

Claim 15

A CMOS integrated circuit programmable logic array comprising: a plurality of inputs for receiving a plurality of input logic signals; a plurality of logic gates each logic gate having a plurality of inputs; a plurality of electrically erasable fuse means each having an output independent of, and not directly connected to, the output of any other electrically erasable fuse means, and the inputs of each logic gate being connected to the outputs of a selected number of electrically erasable fuse means, each logic gate being connected to a different number of electrically erasable fuse means than any other logic gate, for selectively logically coupling selected ones of said inputs to selected ones of said logic gates and for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output; a plurality of program signal control means coupled to selected ones of said logic gates and selected ones of said fuse means, for selectively supplying a programming signal to said selected ones of said fuse means; and a plurality of erase signal control means coupled to selected ones of said fuse means and selected ones of said inputs, for selectively supplying erase signals to said selected ones of said fuse means; wherein said fuse means is selectively programmed into one of two programming states by selective application of predetermined level signals to said inputs, said program signal control means, and said erase signal control means.

Claim 16

A programmable logic array as set out in claim 12 wherein said electrically erasable fuse means operates as a logic inverter when programmed in one of said two programming states and maintains a fixed logic output when in the other of said two programming states.

Claim 17

A programmable logic array as set out in claim 12 wherein said electrically erasable fuse means operates logically as a NAND gate with one NAND logic input the programming state of said fuse means and the other NAND logic input the selected input logic signal supplied to said electrically erasable fuse means.

Claim 18

A programmable logic array as set out in claim 12 wherein said electrically erasable fuse means comprises an electrically erasable transistor and one or more transistors coupled thereto and wherein said electrically erasable transistor is in a D.C. conductive state with approximately constant load characteristics during normal logic operation of said array when said electrically erasable fuse means is programmed in one of said two programming states.

Claim 19

A programmable logic array is set out in claim 12 wherein said program signal control means and said erase signal control means each comprise first and second NAND logic gates coupled to a third NAND logic gate having a two level power supply and providing a three logic level output signal.

Claim 20

A programmable logic array comprising: a plurality of input means for receiving a plurality of input signals; a plurality of logic gates each having a plurality of inputs; a plurality of programmable transistor fuse means, each programmable transistor fuse means having an output independent of, and not connected to, the output of any other fuse means, and each one of said plurality of inputs of each logic gate being connected to a different, selected, output of a programmable transistor fuse means than any other logic gate input for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output, each programmable transistor fuse means having two programming logic states, for providing a relatively constant load conductive current path when in a first one of said two programming states during normal logic operations and a substantially nonconductive path when in the second of said two programming states during normal logic operations; and each means including a programmable transistor and one or more transistor means coupled to said programmable transistor means and said input means and said output means, for providing the NAND logic operation in conjunction with said programmable transistor means on the logic level of said input signal and the logic state of the programmable transistor means and outputting the NAND logical output thereof; a plurality of program signal control means coupled to selected ones of said logic gates and selected ones of said fuse means, for selectively supplying a programming signal to said selected ones of said programmable transistor means; and a plurality of erase signal control means coupled to selected ones of said programmable transistor fuse means and selected ones of said input means, for selectively supplying erase signals to said selected ones of said programmable transistor fuse means; wherein each one of said programmable transistor fuse means is selectively programmed into one of said two programming states by selective application of predetermined level signals to said input means, said program signal control means, and said erase signal control means.

Claim 21

A programmable logic array comprising: a plurality of input means for receiving a plurality of input signals; a plurality of logic gates each having a plurality of inputs; a plurality of programmable transistor fuse means, each programmable transistor fuse means having an output independent of, and not connected to, the output of any other fuse means, and each one of said plurality of inputs of each logic gate being connected to a different, selected, output of a programmable transistor fuse means than any other logic gate input for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output, each programmable transistor fuse means having two programming logic states, for providing a relatively constant load conductive current path when in a first one of said two programming states during normal logic operations and a substantially nonconductive path when in the second of said two programming states during normal logic operations; and each means including a programmable transistor and one or more transistor means coupled to said programmable transistor means and said input means and said output means, for providing the NAND logic operation in conjunction with said programmable transistor means on the logic level of said input signal and the logic state of the programmable transistor means and outputting the NAND logical output thereof; a plurality of program signal control means coupled to selected ones of said logic gates and selected ones of said fuse means, for selectively supplying a programming signal to said selected ones of said programmable transistor means; and a plurality of erase signal control means coupled to selected ones of said programmable transistor fuse means and selected ones of said input means, for selectively supplying erase signals to said selected ones of said programmable transistor fuse means; wherein each one of said programmable transistor fuse means is selectively programmed into one of said two programming states by selective application of predetermined level signals to said input means, said program signal control means, and said erase signal control means.

Claim 22

A programmable logic array as set out in claim 17 wherein said programmable transistor fuse means operates as a logic inverter when programmed in one of said two programming states and maintains a logic high output when in the other of said two programming states.

Claim 23

A programmable logic array as set out in claim 17 wherein said programmable transistor fuse means operates logically as a NAND gate with one NAND logic input the programming state of said programmable transistor fuse means and the other NAND logic input the selected input supplied to said programmable transistor fuse means.

Claim 24

A programmable logic array as set out in claim 17 wherein said logic gates and said programmable transistor fuse means are implemented in a CMOS integrated circuit.

Claim 25

A programmable logic array as set out in claim 17 wherein said programmable transistor means comprises an electrically erasable transistor and said electrically erasable transistor is in a D.C. conductive state with relatively constant load characteristics during normal logic operation of said array when said programmable transistor means is programmed in one of said two programming states.

Claim 26

A programmable logic array comprising: a plurality of inputs for receiving a plurality of input logic signals; a plurality of logic gates each having a plurality of inputs; a plurality of electrically erasable fuse means each having an output independent of, and not directly connected to, the output of any other electrically erasable fuse means, and the inputs of each logic gate being connected to the outputs of a selected number of electrically erasable fuse means, each logic gate being connected to a different number of electrically erasable fuse means than any other logic gate, for selectively logically coupling selected ones of said inputs to selected ones of said logic gates and for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output; a plurality of program signal control means equal in number to said plurality of logic gates and coupled to selected ones of said electrically erasable fuse means, for selectively supplying a programming signal to said selected ones of said fuse means; and a plurality of erase signal control means equal in number to said plurality of inputs and coupled to selected ones of said electrically erasable fuse means, for selectively supplying erase signals to said selected ones of said fuse means; wherein said electrically erasable fuse means is selectively programmed into one of two programming states by selective application of predetermined level signals to said inputs, said program signal control means, and said erase signal control means.

Claim 27

A programmable logic array comprising: a plurality of inputs for receiving a plurality of input logic signals; a plurality of logic gates each having a plurality of inputs; a plurality of electrically erasable fuse means each having an output independent of, and not directly connected to, the output of any other electrically erasable fuse means, and the inputs of each logic gate being connected to the outputs of a selected number of electrically erasable fuse means, each logic gate being connected to a different number of electrically erasable fuse means than any other logic gate, for selectively logically coupling selected ones of said inputs to selected ones of said logic gates and for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output; a plurality of program signal control means equal in number to said plurality of logic gates and coupled to selected ones of said electrically erasable fuse means, for selectively supplying a programming signal to said selected ones of said fuse means; and a plurality of erase signal control means equal in number to said plurality of inputs and coupled to selected ones of said electrically erasable fuse means, for selectively supplying erase signals to said selected ones of said fuse means; wherein said electrically erasable fuse means is selectively programmed into one of two programming states by selective application of predetermined level signals to said inputs, said program signal control means, and said erase signal control means.

Claim 28

A programmable logic array as set out in claim 22 wherein said electrically erasable fuse means operates as a logic inverter when programmed in one of said two programming states and maintains a logic high output when in the other of said two programming states.

Claim 29

A programmable logic array as set out in claim 22 wherein said electrically erasable fuse means operates logically as a NAND gate with one NAND logic input the programming state of said electrically erasable fuse means and the other NAND logic input the selected input supplied to said electrically erasable fuse means.

Claim 30

A programmable logic array as set out in claim 22 wherein said logic gates and said electrically erasable fuse means are implemented in a complementary metal oxide semiconductor integrated circuit.

Claim 31

A programmable logic array as set out in claim 22 wherein said electrically programmable and erasable fuse means comprises an electrically erasable transistor and one or more transistors coupled thereto and wherein said electrically erasable transistor is in a D.C. conductive state with relatively constant load characteristics during normal logic operation of said array when said electrically erasable fuse means is programmed in one of said two programming states.

Claim 32

In a programmable logic gate array of reprogrammable fuses arranged in rows and columns, each reprogrammable fuse comprising: input means for receiving a logic input signal; output means; a first programmable transistor and a second transistor of one conductivity type, a third transistor of complementary conductivity type; each one of said transistors having first and second electrodes defining the ends of a conduction path and a control electrode; said programmable transistor having two programming logic states, for providing a relatively constant load conductive current path when in a first one of said two programming states during normal logic operations and a nonconductive path when in the second of said two programming states during normal logic operations; means serially connecting the conduction paths of said first and second transistors between said output means and a first point of operating potential; means connecting the conduction path of said third transistor between said output means and a second point of operating potential; and means for coupling the control electrodes of said second and third transistors to said input means for providing the NAND logic operation in conjunction with said programmable transistor means on the logic level of said input signal an the logic state of the programmable transistor means and outputting the NAND logical output thereof.

Claim 33

In a programmable logic gate array of reprogrammable fuses arranged in rows and columns, each reprogrammable fuse comprising: input means for receiving a logic input signal; output means; a first programmable transistor and a second transistor of one conductivity type, a third transistor of complementary conductivity type; each one of said transistors having first and second electrodes defining the ends of a conduction path and a control electrode; said programmable transistor having two programming logic states, for providing a relatively constant load conductive current path when in a first one of said two programming states during normal logic operations and a nonconductive path when in the second of said two programming states during normal logic operations; means serially connecting the conduction paths of said first and second transistors between said output means and a first point of operating potential; means connecting the conduction path of said third transistor between said output means and a second point of operating potential; and means for coupling the control electrodes of said second and third transistors to said input means for providing the NAND logic operation in conjunction with said programmable transistor means on the logic level of said input signal an the logic state of the programmable transistor means and outputting the NAND logical output thereof.

Claim 34

In a programmable logic gate array of electrically erasable fuses arranged in rows and columns, each erasable fuse comprising: input means for receiving an input signal; an output; first and second points of operating potential; a programmable transistor having two programming logic states; said programming transistor having first and second electrodes defining the ends of a conduction path and a control electrode; a first transistor of one conductivity type and a second transistor of second conductivity type, each transistor having first and second electrodes defining the ends of a conduction path and a control electrode; means serially connecting the conduction paths of said first transistor and said programmable transistor between said output and said first point of operating potential and means connecting said second transistor between said output and said second point of operating potential and means coupling said input means to the control electrodes of said first and second transistors for providing at said output the logically inverted signal to the input signal provided at said input when said programmable transistor is in a first programming state and providing a fixed logic signal at said output when said programmable transistor is in the second of said two programming states; and means coupled to the control electrode and one end of the conduction path of said programmable transistor for programming said programmable transistor.

Claim 35

In a programmable logic gate array of electrically erasable fuses arranged in rows and columns, each erasable fuse comprising: input means for receiving an input signal; an output; first and second points of operating potential; a programmable transistor having two programming logic states; said programming transistor having first and second electrodes defining the ends of a conduction path and a control electrode; a first transistor of one conductivity type and a second transistor of second conductivity type, each transistor having first and second electrodes defining the ends of a conduction path and a control electrode; means serially connecting the conduction paths of said first transistor and said programmable transistor between said output and said first point of operating potential and means connecting said second transistor between said output and said second point of operating potential and means coupling said input means to the control electrodes of said first and second transistors for providing at said output the logically inverted signal to the input signal provided at said input when said programmable transistor is in a first programming state and providing a fixed logic signal at said output when said programmable transistor is in the second of said two programming states; and means coupled to the control electrode and one end of the conduction path of said programmable transistor for programming said programmable transistor.

Claim 36

A programmable logic array comprising: a plurality of logic input means for receiving a plurality of input logic signals; a plurality of electrically alterable programmable fuse means each having an input and an output and each being programmable into either a first state in which said electrically alterable programmable fuse means operates as a logic inverter or into a second state in which said electrically alterable programmable fuse means provides at its output a preselected fixed logic signal said plurality of electrically alterable programmable fuse means being arranged in "N" rows, each having "M" columns; "N" logic gates, one logic gate per row of electrically alterable programmable fuse means each gate having "M" inputs; means for coupling the outputs of the "M" electrically alterable programmable fuse means of each row to a different one of the "M" inputs of its corresponding logic gate for connecting the output each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output; and programming means for selectively programming said programmable fuse means; where M is an integer greater than two.

Claim 37

A programmable logic array comprising: a plurality of logic input means for receiving a plurality of input logic signals; a plurality of electrically alterable programmable fuse means each having an input and an output and each being programmable into either a first state in which said electrically alterable programmable fuse means operates as a logic inverter or into a second state in which said electrically alterable programmable fuse means provides at its output a preselected fixed logic signal said plurality of electrically alterable programmable fuse means being arranged in "N" rows, each having "M" columns; "N" logic gates, one logic gate per row of electrically alterable programmable fuse means each gate having "M" inputs; means for coupling the outputs of the "M" electrically alterable programmable fuse means of each row to a different one of the "M" inputs of its corresponding logic gate for connecting the output each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output; and programming means for selectively programming said programmable fuse means; where M is an integer greater than two.