US4490812A
Expired / Lapsed
US
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User reprogrammable programmed logic array
Assignee: STMicroelectronics lnc USA
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Filing: 1982-09-30
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Granted: 1984-12-25
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Expires: 2002-09-30
Abstract
Abstract A user-programmable and reprogrammable programmed logic array includes a self-indexing pointer to direct successive input signals to the proper cell within the array. A particular application is that of a ROM patch to correct coding errors in a ROM.
Inventors
- 👤 Daniel C. Guterman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17712
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
121 words
A programmable logic array comprising: a plurality of pattern-matching modules, each of which is responsive to a predetermined pattern of input logical signals for generating a pattern recognition signal; and a plurality of logical output modules, each of which is responsive to a pattern recognition signal from one of said plurality of pattern-matching modules, for outputting a plurality of predetermined output signals, characterized in that: said pattern-matching modules and said logical output modules include a plurality of electrically alterable nonvolatile member elements for storing a predetermined input data pattern, which nonvolatile memory elements may be repeatedly altered; and said predetermined pattern of input logical signals is written into said plurality of pattern-matching modules under the control of a self-indexing pointer circuit.
Claim 2
Dependent Claim
121 words
A programmable logic array comprising: a plurality of pattern-matching modules, each of which is responsive to a predetermined pattern of input logical signals for generating a pattern recognition signal; and a plurality of logical output modules, each of which is responsive to a pattern recognition signal from one of said plurality of pattern-matching modules, for outputting a plurality of predetermined output signals, characterized in that: said pattern-matching modules and said logical output modules include a plurality of electrically alterable nonvolatile member elements for storing a predetermined input data pattern, which nonvolatile memory elements may be repeatedly altered; and said predetermined pattern of input logical signals is written into said plurality of pattern-matching modules under the control of a self-indexing pointer circuit.
Claim 3
Dependent Claim
48 words
A programmable logic array according to claim 1, further characterized in that said self-indexing pointer circuit includes a plurality of pointer cells each of which contain an electrically alterable nonvolatile memory element and means connecting said pointer cell with at least one other pointer cell next in sequence.
References Cited (Backward Citations)
US4034356A
Cited
US4336601A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-25 | 1988-06-25 | 1988-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-25 | 1992-06-25 | 1992-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-25 | 1996-06-25 | 1996-12-25 | $7700.00 | Window Closed / Lapsed |