Patent US4784718A successfully refreshed from Google Patents.
US4784718A
Expired / Lapsed
US
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Method for manufacturing semiconductor device
Assignee: Toshiba Corp
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Filing: 1987-02-19
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Granted: 1988-11-15
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Expires: 2007-02-19
Abstract
Abstract Disclosed is a semiconductor device with its gate electrode and source/drain extraction electrodes being made of the same material on a GaAs substrate, and with its source/drain heavily doped regions, which are formed by doping Se in a lightly doped semiconductor layer on the GaAs substrate, self-aligned with both gate electrode and source/drain extraction electrodes.
Inventors
- 👤 Tatsuro Mitani
- 👤 Toshikazu Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
198 words
A method for manufacturing a semiconductor device comprising the steps of: forming a one-conduction type lightly doped semiconductor layer on a semiconductor substrate; forming a dummy gate on a predetermined region on said lightly doped semiconductor layer; forming a side wall film constituting member on the exposed surface of said lightly doped semiconductor layer, the side wall film constituting member covering said dummy gate; performing an anisotropic etching for said side wall film constituting member to form a side wall film on the side of said dummy gate and to expose the surface of said lightly doped semiconductor layer; introducing predetermined impurities into said lightly doped semiconductor layer, using as a mask said side wall film and said dummy gate, so as to form heavily doped regions; selectively removing said dummy gate so as to expose said lightly doped semiconductor layer therebelow; forming an electrode constituting member on said exposed lightly doped semiconductor layer and said heavily doped regions using the remaining side wall film as a mask; and removing said side wall film and said electrode constituting member deposited thereon so as to form predetermined electrodes on said heavily doped regions and said lightly doped semiconductor layer.
Claim 2
Independent Claim
198 words
A method for manufacturing a semiconductor device comprising the steps of: forming a one-conduction type lightly doped semiconductor layer on a semiconductor substrate; forming a dummy gate on a predetermined region on said lightly doped semiconductor layer; forming a side wall film constituting member on the exposed surface of said lightly doped semiconductor layer, the side wall film constituting member covering said dummy gate; performing an anisotropic etching for said side wall film constituting member to form a side wall film on the side of said dummy gate and to expose the surface of said lightly doped semiconductor layer; introducing predetermined impurities into said lightly doped semiconductor layer, using as a mask said side wall film and said dummy gate, so as to form heavily doped regions; selectively removing said dummy gate so as to expose said lightly doped semiconductor layer therebelow; forming an electrode constituting member on said exposed lightly doped semiconductor layer and said heavily doped regions using the remaining side wall film as a mask; and removing said side wall film and said electrode constituting member deposited thereon so as to form predetermined electrodes on said heavily doped regions and said lightly doped semiconductor layer.
Claim 3
Dependent Claim
19 words
A method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor substrate is made of GaAs.
Claim 4
Dependent Claim
29 words
A method for manufacturing a semiconductor device according to claim 2, wherein the concentration of impurities introduced in said heavily doped regions is 1×10 19 cm -3 or more.
Claim 5
Dependent Claim
37 words
A method for manufacturing a semiconductor device according to claim 2, wherein said electrode constituting member is made in a single layer structure of Al, Au or Ti/Al or in a multi-layer structure consisting of these metals.
Claim 6
Dependent Claim
21 words
A method for manufacturing a semiconductor device according to claim 2, wherein said dummy gate is made of SiO 2 .
Claim 7
Dependent Claim
26 words
A method for manufacturing a semiconductor device according to claim 2, wherein said side wall film constituting member is made of Si 3 N 4 .
Claim 8
Dependent Claim
19 words
A method for manufacturing a semiconductor device according to claim 2, wherein said anisotropic etching is a reactive etching.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |