Patent US4783604A successfully refreshed from Google Patents.
US4783604A
Expired / Lapsed
US
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Buffer circuit for outputting signals of different polarities
Assignee: Toshiba Corp
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Filing: 1987-02-17
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Granted: 1988-11-08
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Expires: 2007-02-17
Abstract
Abstract A buffer circuit comprises first to third CMOS inverters whose input terminals are mutually connected, first and second npn transistors whose bases are commonly connected to an output terminal of the first CMOS inverter and whose emitters are respectively connected to output terminals of the second and third CMOS inverters, fourth and fifth CMOS inverters for inverting the output signals of the first and third CMOS inverters, a third npn transistor whose base and emitter are respectively connected to output terminals of the fourth and fifth CMOS inverters, fourth and fifth npn transistors whose conduction states are controlled by the output signals of the first and fourth CMOS inverters, first and second n-channel MOS transistors which are serially connected to the fourth and fifth npn transistors, respectively, and whose gates are respectively connected to the third and fifth CMOS inverters, and third and fourth n-channel MOS transistors which are respectively connected between the gates of the first and second n-channel MOS transistors and a reference voltage terminal and whose gates are respectively connected to the fourth and first CMOS inverters.
Inventors
- 👤 Masaji Ueno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:44
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/08; H02M1/088; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K5/00; H03K5/15; H03K5/151
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
381 words
A buffer circuit comprising: first and second power source terminals and first and second output nodes; a first delay circuit for receiving on input signal and generating an inverted signal of said input signal from first, second and third output terminals; a second delay circuit for receiving the signals from said first and third output terminals of said first delay circuit and generating inverted signals of these signals from first and second output terminals; first and second bipolar transistors having bases commonly connected to the first output terminal of said first delay circuit and which are connected at one end to the first power source terminal and respectively connected at the other end to the second and third output terminals of said first delay circuit. a third bipolar transistor having a base connected to the first output terminal of said second delay circuit and which is connected at one end to the first power source terminal and connected at the other end to the second output terminal of said second delay circuit; first and second bipolar transistor circuits which are respectively connected between said first power source terminal and the first and second output nodes and are controlled to be set into opposite conduction states in response to the output signals from the first output terminal of said second delay circuit and from the first output terminal of the first delay circuit, respectively; first and second MOS transistors which are respectively connected between the first and second output nodes and said second power source terminal and are controlled to be set into the opposite conduction states in response to the output signals from the third output terminal of said first delay circuit and from the second output terminal of said second delay circuit, respectively; and third and fourth MOS transistors which are respectively connected between the gates of said first and second MOS transistors and said second power source terminal and are respectively controlled to be set into the opposite conduction states in response to the output signals from the first output terminal of said second delay circuit and from the second output terminal of said first delay circuit. wherein output signals in the inversion relation are generated from said first and second output nodes in response to said input signal.
Claim 2
Dependent Claim
381 words
A buffer circuit comprising: first and second power source terminals and first and second output nodes; a first delay circuit for receiving on input signal and generating an inverted signal of said input signal from first, second and third output terminals; a second delay circuit for receiving the signals from said first and third output terminals of said first delay circuit and generating inverted signals of these signals from first and second output terminals; first and second bipolar transistors having bases commonly connected to the first output terminal of said first delay circuit and which are connected at one end to the first power source terminal and respectively connected at the other end to the second and third output terminals of said first delay circuit. a third bipolar transistor having a base connected to the first output terminal of said second delay circuit and which is connected at one end to the first power source terminal and connected at the other end to the second output terminal of said second delay circuit; first and second bipolar transistor circuits which are respectively connected between said first power source terminal and the first and second output nodes and are controlled to be set into opposite conduction states in response to the output signals from the first output terminal of said second delay circuit and from the first output terminal of the first delay circuit, respectively; first and second MOS transistors which are respectively connected between the first and second output nodes and said second power source terminal and are controlled to be set into the opposite conduction states in response to the output signals from the third output terminal of said first delay circuit and from the second output terminal of said second delay circuit, respectively; and third and fourth MOS transistors which are respectively connected between the gates of said first and second MOS transistors and said second power source terminal and are respectively controlled to be set into the opposite conduction states in response to the output signals from the first output terminal of said second delay circuit and from the second output terminal of said first delay circuit. wherein output signals in the inversion relation are generated from said first and second output nodes in response to said input signal.
Claim 3
Dependent Claim
38 words
A buffer circuit according to claim 1, wherein said first delay circuit has first, second, and third CMOS inverters for inverting said input signal and generating output signals from said first, second, and third output terminals thereof, respectively.
Claim 4
Dependent Claim
74 words
A buffer circuit according to claim 2, wherein said second delay circuit includes a fourth CMOS inverter for inverting the output signal from the first output terminal of said first delay circuit and generating an output signal from the first output terminal thereof and a fifth CMOS inverter for inverting the output signal from the third output terminal of said first delay circuit and generating an output signal from the second output terminal thereof.
Claim 5
Dependent Claim
147 words
A buffer circuit according to claim 3, further comprising fourth and fifth bipolar transistors which are respectively connected between the first and second output nodes and the second power source terminal, fifth and sixth MOS transistors which are respectively connected between the base of said fourth bipolar transistor on one hand and said first output node and the second power source terminal on the other, and seventh and eighth MOS transistors which are respectively connected between the base of said fifth bipolar transistor on one hand and said second output node and the second power source terminal on the other, and wherein the gates of said sixth, fifth, eighth, and seventh MOS transistors are respectively connected to the third output terminal of said first delay circuit, the first and second output terminals of said second delay circuit, and the second output terminal of said first delay circuit.
Claim 6
Dependent Claim
24 words
A buffer circuit according to claim 4, wherein each of said first and second bipolar transistor circuits has two bipolar transistors which are Darlington-connected.
Claim 7
Dependent Claim
147 words
A buffer circuit according to claim 2, further comprising fourth and fifth bipolar transistors which are respectively connected between the first and second output nodes and the second power source terminal, fifth and sixth MOS transistors which are respectively connected between the base of said fourth bipolar transistor on one hand and said first output node and the second power source terminal on the other, and seventh and eighth MOS transistors which are respectively connected between the base of said fifth bipolar transistor on one hand and said second output node and the second power source terminal on the other, and wherein the gates of said sixth, fifth, eighth, and seventh MOS transistors are respectively connected to the third output terminal of said first delay circuit, the first and second output terminals of said second delay circuit, and the second output terminal of said first delay circuit.
Claim 8
Dependent Claim
24 words
A buffer circuit according to claim 2, wherein each of said first and second bipolar transistor circuits has two bipolar transistors which are Darlington-connected.
Claim 9
Dependent Claim
74 words
A buffer circuit according to claim 1, wherein said second delay circuit includes a fourth CMOS inverter for inverting the output signal from the first output terminal of said first delay circuit and generating an output signal from the first output terminal thereof and a fifth CMOS inverter for inverting the output signal from the third output terminal of said first delay circuit and generating an output signal from the second output terminal thereof.
Claim 10
Dependent Claim
147 words
A buffer circuit according to claim 1, further comprising fourth and fifth bipolar transistors which are respectively connected between the first and second output nodes and the second power source terminal, fifth and sixth MOS transistors which are respectively connected between the base of said fourth bipolar transistor on one hand and said first output node and the second power source terminal on the other, and seventh and eighth MOS transistors which are respectively connected between the base of said fifth bipolar transistor on one hand and said second output node and the second power source terminal on the other, and wherein the gates of said sixth, fifth, eighth, and seventh MOS transistors are respectively connected to the third output terminal of said first delay circuit, the first and second output terminals of said second delay circuit, and the second output terminal of said first delay circuit.
Claim 11
Dependent Claim
24 words
A buffer circuit according to claim 1, wherein each of said first and second bipolar transistor circuits has two bipolar transistors which are Darlington-connected.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-08 | 1992-05-09 | 1992-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-08 | 1996-05-09 | 1996-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-08 | 2000-05-09 | 2000-11-08 | $7700.00 | Window Closed / Lapsed |