US4618786A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Precharge circuit for enhancement mode memory circuits
Assignee: STMicroelectronics lnc USA
•
Filing: 1984-08-13
•
Granted: 1986-10-21
•
Expires: 2004-08-13
Abstract
Abstract A circuit for precharging the gates of pass transistor that will be subsequently bootstrapped employs a precharge circuit that generates a precharge pulse having magnitude greater than Vcc and distributes the pulse to a number of gate control circuits that raise the pass transistor gate voltages from a quiescent voltage level of Vcc-Vt to Vcc at a time before the bootstrapping signals arrive at the pass transistor.
Inventors
- 👤 Mark G. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:11
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0412; H03K17/04123; G; G11; G11C; G11C7/00; G11C7/12; G11C8/00; G11C8/08; G11C8/18; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
266 words
A field-effect transistor circuit, employing only enhancement transistors, for controlling the passage of at least one controlled signal, after a first predetermined relative time, from an input terminal to an output terminal comprising: at least one pass transistor having a pass transistor gate, an input node and an output node respectively connected to said input terminal and an output terminal, for passing to said input terminal to said output terminal; receiving means for receiving a cycle-initiating signal; pulse-forming means, responsive to said receiving means, for forming a precharge pulse signal having a predetermined duration and a precharge voltage magnitude greater than a power supply voltage magnitude, said precharge pulse signal reaching said precharge voltage magnitude said first predetermined relative time after said cycle-initiating signal; distributing means for distributing said precharge pulse signal to at least one gate control means for controlling the voltage on said pass transistor gate in response to said precharge pulse signal, said gate control means including means for forming an electrical path, for raising said pass transistor gate to said power supply voltage magnitude, between a switching node and said pass transistor gate; and controllable current means, connected to said switching node, for supplying current at a voltage substantially equal to said supply voltage to said switching node at said predetermined relative time after said cycle-initiating signal has been received by said receiving means, whereby said pass transistor gate is brought substantially to said power supply voltage, and also for establishing a path from said pass transistor gate to ground at a second predetermined relative time after said first predetermined relative time.
Claim 2
Dependent Claim
266 words
A field-effect transistor circuit, employing only enhancement transistors, for controlling the passage of at least one controlled signal, after a first predetermined relative time, from an input terminal to an output terminal comprising: at least one pass transistor having a pass transistor gate, an input node and an output node respectively connected to said input terminal and an output terminal, for passing to said input terminal to said output terminal; receiving means for receiving a cycle-initiating signal; pulse-forming means, responsive to said receiving means, for forming a precharge pulse signal having a predetermined duration and a precharge voltage magnitude greater than a power supply voltage magnitude, said precharge pulse signal reaching said precharge voltage magnitude said first predetermined relative time after said cycle-initiating signal; distributing means for distributing said precharge pulse signal to at least one gate control means for controlling the voltage on said pass transistor gate in response to said precharge pulse signal, said gate control means including means for forming an electrical path, for raising said pass transistor gate to said power supply voltage magnitude, between a switching node and said pass transistor gate; and controllable current means, connected to said switching node, for supplying current at a voltage substantially equal to said supply voltage to said switching node at said predetermined relative time after said cycle-initiating signal has been received by said receiving means, whereby said pass transistor gate is brought substantially to said power supply voltage, and also for establishing a path from said pass transistor gate to ground at a second predetermined relative time after said first predetermined relative time.
Claim 3
Dependent Claim
59 words
A circuit according to claim 1, in which at least one of said pass transistors is connected to a row line of a memory array and said gate control means of said at least one pass transistor is located away from said row line, whereby only said pass transistor of said circuit is located close to said row line.
Claim 4
Dependent Claim
73 words
A circuit according to claim 1, in which said controllable current means within said gate control means includes a p-channel transistor connected between a power supply node and said switching node and an n-channel transistor connected between said switching node and ground, whereby current may be supplied to said switching node at said power supply voltage by the application of a low voltage to the gates of said p- and n- channel transistors.
References Cited (Backward Citations)
US3866061A
Cited
US4289973A
Cited
US4401904A
Cited
US4360901A
Cited
US4550264A
Cited
US4521701A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-20 | 1990-04-21 | 1990-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-20 | 1994-04-21 | 1994-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-20 | 1998-04-21 | 1998-10-21 | $7700.00 | Window Closed / Lapsed |