Semiconductor integrated circuit device with memory cells connected to a divided sub-word line

Claim 2

A semiconductor integrated circuit device comprising: a first wiring layer; a first circuit having a first insulated gate field effect transistor and a second wiring layer formed of a material different from said first wiring layer, coupled to the gate electrode of said first insulated field effect transistor, connected to said first wiring layer, and is supplied with a signal from said first wiring layer, said first wiring layer and said second wiring layer being substantially parallel to each other; a second circuit having a second insulated gate field effect transistor, and a third wiring layer formed of a material different from said first wiring layer, coupled to the gate electrode of said second insulated gate field effect transistor, connected to said first wiring layer, and supplied with a signal from said first wiring layer, said first wiring layer and said third wiring layer being substantially parallel to each other; and said second and third wiring layers being divided from each other so as not to be directly electrically connected together and said signal from said first wiring layer being supplied to said second and third wiring layer substantially simultaneously.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said third wiring layer is composed of substantially the same material as said second wiring layer.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein the gate electrodes of a plurality of first insulated gate field effect transistors are coupled to said second wiring layer, and the gate electrodes of a plurality of second insulated gate field effect transistors are coupled to said third wiring layer.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein the gate electrodes of said first insulated gate field effect transistors and said second wiring layer are formed as a unitary structure, and the gate electrodes of said second insulated field effect transistors and said third wiring layer are formed as a unitary structure.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein said first wiring layer comprises an aluminum layer, and said second and third wiring layers comprises electrically conductive polycrystalline silicon layers.

Claim 7

A semiconductor integrated circuit device according to claim 1, wherein said first wiring layer is formed of a material which has lower electrical resistivity than said second and third wiring layers.

Claim 8

A semiconductor integrated circuit device according to claim 2, wherein provision is further made of a fourth wiring layer for coupling said first wiring layers and said second wiring layer together, and a fifth wiring layer for coupling said first wiring layer and said third wiring layer together.

Claim 9

A semiconductor integrated circuit device according to claim 7, wherein said fourth and fifth wiring layers are formed of the same material as said first wiring layer.

Claim 10

A semiconductor integrated circuit device according to claim 8, wherein said first, fourth and fifth wiring layers are formed of aluminum.

Claim 11

A semiconductor integrated circuit device according to claim 8, wherein said first, fourth and fifth wiring layers are formed of aluminum and said second and third wiring layers are made of electrically conductive polycrystalline silicon.

Claim 12

A semiconductor integrated circuit device comprising: a plurality of memory cell columns each of which includes: a first wiring layer; a first circuit which has a memory cell that includes a first insulated gate field effect transistor, and has a second wiring layer formed of a material different from said first wiring layer, coupling to the gate electrode of said first insulated gate field effect transistor, connected to said first wiring layer, and supplied with a signal from said first wiring layer, said first wiring layer and said second wiring layer being substantially parallel to each other; and a second circuit which has a memory cell that includes a second insulated gate field effect transistor, and has a third wiring layer formed of a material different from said first wiring layer, coupled to the gate electrode of said second insulated gate field effect transistor, connected to said first wiring layer, and is supplied with a signal from said first wiring layer, said first wiring layer and said third wiring layer being substantially parallel to each other; said second and third wiring layer being divided from each other so as to not be directly connected together and asid signal from said first wiring layer is supplied to said second and third wiring layers substantially simultaneously; a select circuit which selectively supplies a signal to selected ones of said plurality of first wiring layers; and wherein memory cell columns are selected out of said plurality of memory cell columns in accordance with said signal supplied by said select circuit.

Claim 13

A semiconductor integrated circuit device comprising: a plurality of memory cell columns each of which includes: a first wiring layer; a first circuit which has a memory cell that includes a first insulated gate field effect transistor, and has a second wiring layer formed of a material different from said first wiring layer, coupling to the gate electrode of said first insulated gate field effect transistor, connected to said first wiring layer, and supplied with a signal from said first wiring layer, said first wiring layer and said second wiring layer being substantially parallel to each other; and a second circuit which has a memory cell that includes a second insulated gate field effect transistor, and has a third wiring layer formed of a material different from said first wiring layer, coupled to the gate electrode of said second insulated gate field effect transistor, connected to said first wiring layer, and is supplied with a signal from said first wiring layer, said first wiring layer and said third wiring layer being substantially parallel to each other; said second and third wiring layer being divided from each other so as to not be directly connected together and asid signal from said first wiring layer is supplied to said second and third wiring layers substantially simultaneously; a select circuit which selectively supplies a signal to selected ones of said plurality of first wiring layers; and wherein memory cell columns are selected out of said plurality of memory cell columns in accordance with said signal supplied by said select circuit.

Claim 14

A semiconductor integrated circuit device according to claim 11, wherein said first wiring layer is formed of a material which has a lower electrical resisitivity than said second and third wiring layers.

Claim 15

A semiconductor integrated circuit device according to claim 11, wherein said third wiring layer is composed of substantially the same material as said second wiring layer.

Claim 16

A semiconductor integrated circuit device according to claim 13, wherein the gate electrodes of a plurality of first insulated gate field effect transistors are coupled to said second wiring layer, and the gate electrodes of a plurality of second insulated gate field effect transistors are coupled to said third wiring layer.

Claim 17

A semiconductor integrated circuit device according to claim 14, wherein said second wiring layer and the gate electrodes of said first insulated gate field effect transistors are formed as a unitary structure, and said third wiring layer and the gate electrodes of said second insulated gate field effect transistors are formed as a unitary structure.

Claim 18

A semiconductor integrated circuit device according to claim 15, wherein said insulated gate field effect transistor included in a memory cell has an output electrode to which a data line is coupled, and a ground electrode to which ground potential of the circuit is supplied.

Claim 19

A semiconductor integrated circuit device according to claim 16, wherein provision is further made of precharging means for precharging said output electrodes.

Claim 20

A semiconductor integrated circuit device according to claim 17, wherein said first wiring layer comprises an aluminum layer, and said second and third wiring layers comprise electrically conductive polycrystalline silicon layers.

Claim 21

A semiconductor integrated circuit device according to claim 15, wherein the memory cell further includes memory means having an input/output terminal to store data, and the first or second insulated gate field effect transistor contained in the memory cell has a first input/output electrode coupled to the input/output terminal of said memory means and a second input/output electrode coupled to the data line.

Claim 22

A semiconductor integrated circuit device according to claim 19, wherein said memory means comprises a flip-flop circuit having a pair of input/output terminals, and either one of said pair of input/output terminals is coupled to said input/output terminal.

Claim 23

A semiconductor integrated circuit device according to claim 19, wherein said first wiring layer comprises an aluminum layer, and said second and third wiring layers comprise electrically conductive polycrystalline silicon layers.

Claim 24

A semiconductor integrated circuit device comprising: a first wiring layer; a first circuit having a plurality of first insulated gate field effect transistors and a second wiring layer formed of a material different from said first wiring layer, having a higher resitivity than said first wiring layer, coupled to the gate electrodes of each of said first insulated gate field effect transistor, connected to the first wiring layer, and supplied with a signal from said first wiring layer, said first and said second wiring layers being substantially parallel to each other; a second circuit having a plurality of second insulated gate field effect transistor, and a third wiring layer formed of a material different form said first wiring layer, having a higher resistivity than said first wiring layer, coupled to the gate electrodes of each of said second insualted gate field effect transistors, connected to the first wiring layer, and supplied with a signal from said first wiring layer substantially simultaneously substantially simultaneously with the supply of a signal from said first wiring layer to said second wiring layer, said first and said third wiring layer being substantially parallel to each other; wherein said third wiring layer is composed of the same material as said second wiring layer; the gate electrodes of said first insulated gate field effect transistors and said second wiring layer are formed as a unitary structure, and the gate electrodes of said second insulated gate field effect transistors and said third wiring layer are formed as a unitary structure with the second and third layers being divided so as to not be directly connected together; and wherein provision is further made of a fourth wiring layer for coupling said first wiring layer and said second wiring layer together, and a fifth wiring layer for coupling said first wiring layer and said third wiring layer together, said fourth and fifth wiring layers being formed of the same material as said first wiring layer.

Claim 25

A semiconductor integrated circuit device comprising: a first wiring layer; a first circuit having a plurality of first insulated gate field effect transistors and a second wiring layer formed of a material different from said first wiring layer, having a higher resitivity than said first wiring layer, coupled to the gate electrodes of each of said first insulated gate field effect transistor, connected to the first wiring layer, and supplied with a signal from said first wiring layer, said first and said second wiring layers being substantially parallel to each other; a second circuit having a plurality of second insulated gate field effect transistor, and a third wiring layer formed of a material different form said first wiring layer, having a higher resistivity than said first wiring layer, coupled to the gate electrodes of each of said second insualted gate field effect transistors, connected to the first wiring layer, and supplied with a signal from said first wiring layer substantially simultaneously substantially simultaneously with the supply of a signal from said first wiring layer to said second wiring layer, said first and said third wiring layer being substantially parallel to each other; wherein said third wiring layer is composed of the same material as said second wiring layer; the gate electrodes of said first insulated gate field effect transistors and said second wiring layer are formed as a unitary structure, and the gate electrodes of said second insulated gate field effect transistors and said third wiring layer are formed as a unitary structure with the second and third layers being divided so as to not be directly connected together; and wherein provision is further made of a fourth wiring layer for coupling said first wiring layer and said second wiring layer together, and a fifth wiring layer for coupling said first wiring layer and said third wiring layer together, said fourth and fifth wiring layers being formed of the same material as said first wiring layer.

Claim 26

A semiconductor integrated random access memory formed in a semiconductor substrate comprising: a plurality of aluminum word lines disposed substantially parallel with each other; a plurality of divided sub-word lines made of a material having a conductivity lower than that of the word lines, each divided sub-word line being disposed substantially parallel with each of the aluminum word lines which are connected thereto to receive a signal therefrom and each of said divided sub-word lines, which is connected to one of said aluminum word lines, is substantially simultaneously supplied with the signal from said one of said aluminum word lines and the individual divided word lines not being directly connected together.

Claim 27

A semiconductor integrated random access memory formed in a semiconductor substrate comprising: a plurality of aluminum word lines disposed substantially parallel with each other; a plurality of divided sub-word lines made of a material having a conductivity lower than that of the word lines, each divided sub-word line being disposed substantially parallel with each of the aluminum word lines which are connected thereto to receive a signal therefrom and each of said divided sub-word lines, which is connected to one of said aluminum word lines, is substantially simultaneously supplied with the signal from said one of said aluminum word lines and the individual divided word lines not being directly connected together.

Claim 28

A semiconductor integrated random access memory as recited in claim 23 wherein the divided sub-word lines are formed of a layer of polycrystalline silicon.

Claim 29

A semiconductor integrated random access memory as recited in claim 24, further comprising: an aluminum interconnection layer disposed below the aluminum word lines.

Claim 30

A semiconductor integrated random access memory as recited in claim 24, further comprising: an aluminum interconnection layer disposed below the aluminum word lines.

Claim 31

A semiconductor integrated memory device formed in a semiconductor substrate comprising: a plurality of aluminum word lines disposed substantially parallel with each other; a plurality of divided sub-word lines disposed substantially parallel with each of the aluminum word lines and connected thereto to receive a signal therefrom and each of said divided sub-word lines which is connected to one of said aluminum word lines is substantially simultaneously supplied with the signal from said one of said aluminum word lines and the individual divided word lines not being directly connected together.

Claim 32

A semiconductor integrated memory device formed in a semiconductor substrate comprising: a plurality of aluminum word lines disposed substantially parallel with each other; a plurality of divided sub-word lines disposed substantially parallel with each of the aluminum word lines and connected thereto to receive a signal therefrom and each of said divided sub-word lines which is connected to one of said aluminum word lines is substantially simultaneously supplied with the signal from said one of said aluminum word lines and the individual divided word lines not being directly connected together.

Claim 33

A semiconductor integrated memory device recited in claim 27, further comprising: an aluminum interconnection layer disposed below the aluminum word lines.

Claim 34

A semiconductor integrated memory device, recited in claim 27, wherein the divided sub-word lines are formed of a layer of polycrystalline silicon.

Claim 35

A semiconductor integrated memory device recited in claim 25, further comprising: an aluminum interconnection layer disposed below the aluminum word lines.