US4780629A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Network for processing high-bit-width data comprising a transmitter and a plurality of receivers
Assignee: Wincor Nixdorf International GmbH
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Filing: 1986-09-18
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Granted: 1988-10-25
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Expires: 2006-09-18
Abstract
Abstract In order to enable the control of plurality of receivers in CML technology comprising two or three levels of series gating by way of a transmitter whose maximum fanout is smaller than the total number of receivers, the emitter followers provided for level shifting of the control signal for a differential amplifier of the second or third series-gated switch level in each receiver are omitted and are replaced by a common emitter follower having increased performance capability for a respective group of n2 receivers. The invention finds application in 2-bit multiplexers and register stages.
Inventors
- 👤 Bernhard Unger
- 👤 Rainer Rauschert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:49
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6221; H03K17/6228; H03K17/603; H03K17/6257; H03K17/6264
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
128 words
A network constructed in CML circuit technology for processing data having a large data bit width greater than 8, comprising: a transmitter having an output with a predetermined loadability; a plurality of receivers each including differential amplifiers connected for multi-level series gating, the total number n of receivers exceeding the loadability of said transmitter and the number n of receivers being divided into groups of n2 receivers in each group; a common emitter follower cell of increased performance capability of n fold of the performance capability of an individual emitter follower for each of said groups; and each of said common emitter follower cells comprising an input connected to the output of said transmitter and each said common emitter follower cell supplying an individual group of n2 receivers.
Claim 2
Dependent Claim
128 words
A network constructed in CML circuit technology for processing data having a large data bit width greater than 8, comprising: a transmitter having an output with a predetermined loadability; a plurality of receivers each including differential amplifiers connected for multi-level series gating, the total number n of receivers exceeding the loadability of said transmitter and the number n of receivers being divided into groups of n2 receivers in each group; a common emitter follower cell of increased performance capability of n fold of the performance capability of an individual emitter follower for each of said groups; and each of said common emitter follower cells comprising an input connected to the output of said transmitter and each said common emitter follower cell supplying an individual group of n2 receivers.
Claim 3
Dependent Claim
34 words
The network of claim 1, wherein: the loadability of the transmitter is n1 for supplying an address bit and n>n1 two-bit multiplexers are the receivers and address inputs of each multiplexer are receiver inputs.
Claim 4
Dependent Claim
34 words
The network of claim 1, wherein: the loadability of the transmitter is n1 for supplying clock pulses and n>n1 register stages are the receivers and clock inputs of each register stage are receiver inputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-25 | 1992-04-25 | 1992-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-25 | 1996-04-25 | 1996-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-25 | 2000-04-25 | 2000-10-25 | $7700.00 | Window Closed / Lapsed |