US4532440A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip-flop in current mode logic controlled by a transfer clock with auxiliary current applied to differential amplifier
Assignee: Siemens AG
•
Filing: 1982-11-03
•
Granted: 1985-07-30
•
Expires: 2002-11-03
Abstract
Abstract In order to avoid noise pulses which occur at the end of a clock pulse given a low signal level at the output of a clock-controlled flip-flop in ECL technology, an auxiliary current which is small in comparison to the primary current is supplied to a differential amplifier which is in a currentless condition during a clock pulse. As a result, the differential amplifier can be set to the respectively correct switch state before the end of the clock pulse.
Inventors
- 👤 Claude Barre
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:25
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/013; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
168 words
In a flip-flop for operation in the current mode logic technique and controlled by a transfer clock and of the type having a first differential amplifier with emitter-coupled transistors fed by a primary current source connected between an operating potential and the emitters of the emitter-coupled transistors, and second and third differential amplifiers each having emitter-coupled transistors whose emitters are connected to respective collector circuits of the emitter-coupled transistors of the first differential amplifier, and in which the transfer clock is applied to the base of a first emitter-coupled transistor of the first differential amplifier and in which the base of the second emitter-coupled transistor of the first differential amplifier is connected to a fixed reference potential, the improvement therein comprising: an auxiliary current source for producing an auxiliary current, said auxiliary current source being connected between the emitters of the emitter-coupled transistors of the third differential amplifier and the operating potential and providing a current of 5%-10% of the primary current supplied by the primary current source.
Claim 2
Dependent Claim
168 words
In a flip-flop for operation in the current mode logic technique and controlled by a transfer clock and of the type having a first differential amplifier with emitter-coupled transistors fed by a primary current source connected between an operating potential and the emitters of the emitter-coupled transistors, and second and third differential amplifiers each having emitter-coupled transistors whose emitters are connected to respective collector circuits of the emitter-coupled transistors of the first differential amplifier, and in which the transfer clock is applied to the base of a first emitter-coupled transistor of the first differential amplifier and in which the base of the second emitter-coupled transistor of the first differential amplifier is connected to a fixed reference potential, the improvement therein comprising: an auxiliary current source for producing an auxiliary current, said auxiliary current source being connected between the emitters of the emitter-coupled transistors of the third differential amplifier and the operating potential and providing a current of 5%-10% of the primary current supplied by the primary current source.
Claim 3
Dependent Claim
61 words
The improved flip-flop of claim 1, wherein the primary current source and the auxiliary current source each comprise: a transistor including a collector connected to the respective differential amplifier, a base connected in common with the like base of the transistor of the other current source, and an emitter; and an emitter resistor connected between said emitter and the operating potential.
Claim 4
Dependent Claim
44 words
The improved flip-flop of claim 2, wherein said emitter resistor of said auxiliary current source is connected to said emitter of said transistor of said primary current source and by way of said emitter resistor of said primary current source to the operating potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-29 | 1989-01-28 | 1989-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-29 | 1993-01-28 | 1993-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-29 | 1997-01-28 | 1997-07-30 | $7700.00 | Window Closed / Lapsed |