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US4773084A
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Synchronizing pattern
Assignee: Deutsche Thomson OHG
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Filing: 1986-02-18
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Granted: 1988-09-20
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Expires: 2006-02-18
Abstract
Abstract For the transmission of synchronizing information for a PCM signal transmitted in biphase code, a synchronizing pattern is provided which is composed of a biphase signal that has been shifted by one-half bit period relative to the data portion of the transmitted signal.
Inventors
- 👤 Werner Scholz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 01:21
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/06; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
74 words
In a method of transmitting a pulse code modulated data signal train in biphase code having a complete sequence of level changes and a sequence of level changes having gaps, and including periodically inserting a synchronizing pattern into the data signal train prior to transmission; the improvement wherein said step of inserting includes inserting a synchronizing pattern which comprises a biphase signal which is shifted by one-half bit period relative to said data signal.
Claim 2
Dependent Claim
74 words
In a method of transmitting a pulse code modulated data signal train in biphase code having a complete sequence of level changes and a sequence of level changes having gaps, and including periodically inserting a synchronizing pattern into the data signal train prior to transmission; the improvement wherein said step of inserting includes inserting a synchronizing pattern which comprises a biphase signal which is shifted by one-half bit period relative to said data signal.
Claim 3
Dependent Claim
52 words
A method as defined in claim 1, wherein said shifted biphase signal of said synchronizing pattern produces at least one gap in the complete level change sequence of the transmitted biphase signal while producing no spacings between adjacent level changes other than one-half or one bit period in the total transmitted signal.
Claim 4
Dependent Claim
39 words
A method as defined in claim 2, wherein said biphase code is a biphase level code; and said synchronizing pattern includes a plurality of bits with the last bit being identical with the bit immediately preceding said synchronizing pattern.
Claim 5
Dependent Claim
32 words
A method as defined in claim 3 wherein said shifted biphase signal of said synchronizing pattern produces a plurality of gaps in said complete level change sequence of said transmitted biphase signal.
Claim 6
Dependent Claim
18 words
A method as defined in claim 1 wherein said synchronizing pattern is composed of at least two bits.
Claim 7
Dependent Claim
25 words
A method as defined in claim 1 wherein said synchronizing pattern is composed of at least three bits and always has the same signal sequence.
Claim 8
Dependent Claim
26 words
A method as defined in claim 1 wherein said data signal train is a biphase level signal and said synchronizing pattern is composed of three bits.
Claim 9
Dependent Claim
33 words
A method as defined in claim 1 wherein said synchronizing pattern includes at least two sequential bits, each having a length of one bit period, which are inverted with respect to one another.
Claim 10
Dependent Claim
58 words
A method as defined in claim 8 wherein: said biphase signal of said data signal train is a biphase level signal; said synchronizing pattern includes a further bit following said at least two bits; and said further bit is identical with the bit of the transmitted signal immediately preceding said at least two bits of said synchronizing pattern.
Claim 11
Dependent Claim
67 words
A method as defined in claim 1 wherein: said biphase code is a biphase level code; and said synchronizing pattern includes an even number of sequential bits, each having a length of one bit period, which are inverted with respect to one another, and a further bit immediately following said even number of bits and being identical to the bit immediately preceding said even number of bits.
Claim 12
Dependent Claim
14 words
A method as defined in claim 10 wherein said synchronizing pattern includes three bits.
References Cited (Backward Citations)
US3631463A
Cited
US3903504A
Cited
US3898388A
Cited
US4025720A
Cited
US4063291A
Cited
US4124778A
Cited
US4232387A
Cited
EP0081750A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-20 | 1992-03-21 | 1992-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-20 | 1996-03-21 | 1996-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-20 | 2000-03-21 | 2000-09-20 | $7700.00 | Window Closed / Lapsed |