Phase inversion synchronization

Claim 2

In the method of synchronizing a time division multiplexing system of the type in which data manifestations from a plurality of sources are interleaved with one another in streams of binary non-return to zero manifestations of two different, related kinds respectively representing binary ONEs and ZEROs, in cyclically repetitive sequential frames, each frame comprising a sequence of bit times, the step of: providing a transition from a data manifestation of one kind to a data manifestation of the opposite kind at substantially the center of a bit time having the same position in the sequence of bit times within each frame, on the condition however that the data manifestation next preceding said bit time in said sequence is of a kind opposite to that of the data manifestation next succeeding said bit time in said sequence.

Claim 3

In a time division multiplexing system of the type in which data manifestations from a plurality of sources are interleaved with one another in streams of manifestations comprising a plurality of cyclically repetitive sequential frames, the data being represented by manifestations of two different, related kinds respectively representing binary ONEs and ZEROs, phase inversion synchronization apparatus comprising: means for cyclically presenting successive frames of data manifestations, in binary non return to zero format, each of said frames of data manifestations including a sequence of bit times, one of the bit times of each of said frames being designated as a framing bit time; and selective transition means responsive to data bit manifestations of opposite kinds in bit times immediately preceding and immediately succeeding each of said framing bit times in said stream for causing a selective transition from one manifestation kind to the other manifestation kind at a time substantially centrally disposed in the related one of said framing bit times.

Claim 4

In a time division multiplexing system of the type in which data manifestations from a plurality of sources are interleaved with one another in streams of manifestations comprising a plurality of cyclically repetitive sequential frames, the data being represented by manifestations of two different, related kinds respectively representing binary ONEs and ZEROs, phase inversion synchronization apparatus comprising: means for cyclically presenting successive frames of data manifestations, in binary non return to zero format, each of said frames of data manifestations including a sequence of bit times, one of the bit times of each of said frames being designated as a framing bit time; and selective transition means responsive to data bit manifestations of opposite kinds in bit times immediately preceding and immediately succeeding each of said framing bit times in said stream for causing a selective transition from one manifestation kind to the other manifestation kind at a time substantially centrally disposed in the related one of said framing bit times.

Claim 5

Synchronization apparatus according to claim 2 wherein said selective transition means comprises a data clock establishing data bit times, a three stage shift register operating in response to said date clock, means for comparing the data manifestations in the first and third stages of said shift register and providing a delayed shift signal when said data manifestations are of opposite kinds, and means responsive to said delayed shift signal for causing the manifestation in the third stage of said shift register to be shifted out of said shift register at a time which is one-half data-bit time delayed with respect to said data clock and within one of said framing bit times.

Claim 6

Synchronization apparatus according to claim 3 wherein said selective transition means further comprises means responsive to the data content of said shift register for causing the content of the second stage of said shift register to assume the same kind of data manifestation as the content of the third stage of said shift register at a time when said second stage of said shift register corresponds with said framing bit time.

Claim 7

Synchronization apparatus according to claim 3 including a selective inverter responsive to said data clock for shifting said shift register, said selective inverter responsive to said delayed shift signal for inverting the data clock applied to said shift register.

Claim 8

A time division multiplexing system including: transmitter apparatus comprising phase inversion synchronization apparatus according to claim 2 and means responsive thereto for transmitting data manifestations therefrom; and receiver apparatus adapted to receive transmissions from said transmitter apparatus and including a phase-locked loop responsive to said selective transition for generating framing signals synchronized therewith.