US3903504A
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Binary phase digital decoding system
Assignee: Singer Co
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Filing: 1974-03-20
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Granted: 1975-09-02
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Expires: 1994-03-20
Abstract
Abstract A digital decoding system is provided which is capable of decoding binary phase modulated digital data streams of arbitrary bit length. The system decodes data signals of either polarity following or preceding a synchronizing signal. The decoder system includes a tri-state signal detector logic circuit which is strobed at a predetermined rate by a high frequency clock, and appropriate registers and associated logic circuitry for storing the resulting binary synchronizing and data signals and for ultimately recovering the digital data. The system also includes logic circuitry for recognizing the synchronizing signal and its polarity.
Inventors
- 👤 R Timothy Rogers
- 👤 Fred Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 01:42
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; H04L7/00; H04L7/04; H04L7/06; H04L7/041; H04L7/042
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
209 words
A digital decoding system for recovering digital data from a binary phase modulated input signal which includes multi-bit data words and associated synchronizing signals, in which each binary bit in the data words, and each synchronizing signal, is identified by a pulse of one polarity followed by a pulse of opposite polarity, and in which the pulses forming the synchronizing signals are of different duration from the pulses forming the bits of the data words, said decoding system comprising: input circuit means including a detector circuit for producing a first output for each pulse of one polarity in the input signal, for producing a second output for each pulse of opposite polarity in the input signal; a strobe clock signal generator; said detector circuit comprising a tri-state circuit, which applies a reset signal to said circuitry for detecting said synchronizing signals and for decoding the data bits of the multi-bit data words for at least one strobe clock time for each transistion of the input signal between one pulse polarity and the opposite pulse polarity; and circuitry coupled to said detector circuit and to said strobe signal generator for detecting said synchronizing signals and for decoding the data bits of the multi-bit data words associated with said synchronizing signals.
Claim 2
Dependent Claim
209 words
A digital decoding system for recovering digital data from a binary phase modulated input signal which includes multi-bit data words and associated synchronizing signals, in which each binary bit in the data words, and each synchronizing signal, is identified by a pulse of one polarity followed by a pulse of opposite polarity, and in which the pulses forming the synchronizing signals are of different duration from the pulses forming the bits of the data words, said decoding system comprising: input circuit means including a detector circuit for producing a first output for each pulse of one polarity in the input signal, for producing a second output for each pulse of opposite polarity in the input signal; a strobe clock signal generator; said detector circuit comprising a tri-state circuit, which applies a reset signal to said circuitry for detecting said synchronizing signals and for decoding the data bits of the multi-bit data words for at least one strobe clock time for each transistion of the input signal between one pulse polarity and the opposite pulse polarity; and circuitry coupled to said detector circuit and to said strobe signal generator for detecting said synchronizing signals and for decoding the data bits of the multi-bit data words associated with said synchronizing signals.
Claim 3
Dependent Claim
52 words
The digital decoding system defined in claim 1, in which said circuitry includes a synchronizing signal detector register responsive to the output of said detector circuit and to strobe pulses from said clock signal generator for producing an output pulse for each pulse forming the aforesaid synchronizing signals in the input signal.
Claim 4
Dependent Claim
104 words
The digital decoding system defined in claim 2, in which said input signal includes positive synchronizing signals each formed by a positive pulse followed by a negative pulse, and negative synchronizing signals each formed by a negative pulse followed by a positive pulse, and in which said circuitry includes network means responsive to the first and second outputs from said detector circuit and to the output pulses from said synchronizing signal detector register for producing a first output in response to a positive synchronizing signal in said input and for producing a second output in response to a negative synchronizing signal in said input.
Claim 5
Dependent Claim
46 words
The digital decoding system defined in claim 2, in which said detector circuit applies a reset signal to said synchronizing signal detector register for at least one strobe clock time for each transition of the input signal between one pulse polarity and the opposite pulse polarity.
Claim 6
Dependent Claim
93 words
The digital decoding system defined in claim 1, in which said circuitry includes a data detector register responsive to the output of said detector circuit and to strobe pulses from said clock signal generator for producing an output pulse for each pulse forming the binary bits of the data words in the input signal, and network means responsive to the first and second outputs from said detector circuit and to the output pulses from said data detector register for producing decoded data bits corresponding to the multi-bit data words of the input signal.
Claim 7
Dependent Claim
45 words
The digital decoding system defined in claim 5, in which said detector circuit applies a reset signal to said data detector register for at least one strobe clock time for each transition of the input signal between one pulse polarity and the opposite pulse polarity.
Claim 8
Dependent Claim
36 words
The digital decoding system defined in claim 5, in which said circuitry includes a decoding circuit coupled to said network means for producing a data clock signal synchronized with the data bits of the input signal.
Claim 9
Dependent Claim
50 words
The digital decoding system defined in claim 7, and which includes a timer circuit connected to said strobe clock signal generator and to the output of said decoding circuit to produce an output in the event the data clock signal beocmes missynchronized with the data bits of the input signal.
Claim 10
Dependent Claim
57 words
The digital decoding system defined in claim 3, in which said network means includes a synchronizing signal scorecard register for receiving the output pulses from the synchronizing signal detector register and the outputs from the detector circuit, and a decoding circuit coupled to said scorecard register for producing the first and second outputs of the network means.
Claim 11
Dependent Claim
35 words
The digital decoding system defined in claim 5, in which said network means includes a data scorecard register for receiving the outputs from the detector circuit and the output pulses from said data detector register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-01 | 1979-03-03 | 1979-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-01 | 1983-03-03 | 1983-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-01 | 1987-03-03 | 1987-09-02 | $7700.00 | Window Closed / Lapsed |