Stud-defined integrated circuit structure

Claim 2

A free-standing integrated semiconductor structure comprising: a semiconductor body; a submicron-wide protrusion of moncrystalline semiconductor material extending upwardly from and integral with said body said material including a semiconductor device, said protrusion having a lower section of a first conductivity type and an upper section of a second conductivity type, said upper section including top and bottom portions of a similar first width and a middle portion of a second width larger than said first width, said lower section having a width comparable to said first width; insulator sidewalls of dissimilar thickness provided on said upper and lower sections of said protrusion, the thickness of said insulator on said top and bottom portions and said lower section being of an equal first thickness and the thickness of said insulator on said middle portion being of a second thickness smaller than the first thickness, said insulator of second thickness having openings exposing localized regions of said middle portion, whereby said protrusion has substantially vertical walls; and electrical contacts made to said localized regions.

Claim 3

The structure as recited in claim 1 wherein said semiconductor material is epitaxial silicon.

Claim 4

The structure as recited in claim 2 further comprising doped regions of said first conductivity type embedded in the outer walls of said middle portion, said doped regions constituting the emitter and collector of a lateral transistor and the region between said doped regions constituting the base of said transistor.

Claim 5

The structure as in claim 3 wherein said emitter and collector are formed in a boxed-in relationship with said insulator sidewalls surrounding said emitter and collector for enhancing the transistor gain.

Claim 6

The structure as recited in claim 3 further comprising electrical contacts to said emitter and collector provided on said vertical walls and contact to said base provided on said top portion.

Claim 7

The structure as recited in claim 4 further comprising first conductivity type dopant gradients formed in said top portion and said bottom portion, said gradient in the top portion including a first dopant concentration in upper strata of said top portion and a second dopant concentration in lower strata of said top portion, said first concentration being higher than said second concentration, said gradient in said bottom portion being a mirror image of said gradient in the top portion.

Claim 8

The structure as recited in claim 1 further comprising: doped regions of said first conductivity type embedded in the outer walls of said middle portion and the surface of said top portion; and a gate electrode formed on the surface of said top portion, whereby said structure constitutes a junction field effect transistor.

Claim 9

The structure as recited in claim 1 further comprising: doped source and drain regions of said first conductivity type embedded in the outer walls of said middle portion; a gate insulator layer formed on the surface of said top portion; and a conductive gate electrode formed on said gate insulator layer, whereby said structure constitutes an insulated field effect transistor.

Claim 10

The structure as recited in claim 1 further comprising at least one highly doped second conductivity type doped region embedded in said middle portion and a metal contact formed on said top portion whereby said second conductivity type doped region and the remainder of said middle portion constitute the cathode and said metal contact formed on said top portion constitute the anode of a Schottky barrier diode.

Claim 11

The structure as recited in claim 1 further comprising a plurality of electrical contacts formed at a mutal separation on said top portion whereby said structure constitutes a resistor.

Claim 12

The structure as recited in claim 1 further comprising electrical contacts formed on opposite sides of said middle portion of the protrusion whereby said structure constitutes a resistor.

Claim 13

The structure as recited in claim 8 further comprising electrical contacts to said source and drain regions.

Claim 14

The structure as recited in claim 9 further comprising electrical contacts to the elements of said diode provided on said vertical walls.

Claim 15

The integrated circuit as recited in claim 7 wherein said dielectrically isolating material is silicon dioxide.

Claim 16

An integrated circuit semiconductor device comprising: a fully dielectrically isolated semiconductor field effect transistor pedestal device; said pedestal being of submicron width and including a bottom section of dielectrically isolating material, a top section of monocrystalline semiconductor material and a plurality of sides, said top section including a substantially planar top surface; a laterally central portion of said top section of said pedestal being the first conductivity type channel region of said field effect transistor, said central portion having side regions of said semiconductor material; source and drain regions of a second conductivity type located in a mutually opposing relationship in said side regions of said central channel region; a dielectrically insulating layer on said top surface; a gate electrode overlying said insulating layer; a dielectrically isolating layer on the pedestal sides except for localized regions thereof which are not covered by said isolating layer; and electrically containing means to said source and drain through the said localized regions.

Claim 17

An integrated circuit semiconductor device comprising: a fully dielectrically isolated semiconductor field effect transistor pedestal device; said pedestal being of submicron width and including a bottom section of dielectrically isolating material, a top section of monocrystalline semiconductor material and a plurality of sides, said top section including a substantially planar top surface; a laterally central portion of said top section of said pedestal being the first conductivity type channel region of said field effect transistor, said central portion having side regions of said semiconductor material; source and drain regions of a second conductivity type located in a mutually opposing relationship in said side regions of said central channel region; a dielectrically insulating layer on said top surface; a gate electrode overlying said insulating layer; a dielectrically isolating layer on the pedestal sides except for localized regions thereof which are not covered by said isolating layer; and electrically containing means to said source and drain through the said localized regions.

Claim 18

An integrated circuit semiconductor device comprising: a fully dielectrically isolated semiconductor junction field effect transistor pedestal device; said pedestal including a bottom section of dielectrically isolating material, a top section of monocrystalline semiconductor material and a plurality of sides, said top section including a laterally central portion of a first conductivity type channel region of said transistor and a second conductivity type surface region of a second conductivity type, said central portion having side regions of said semiconductor material; said surface region of said top section being the gate region of said field effect transistor; source and drain regions of a second conductivity type located in a mutually opposing relationship in said side regions; a gate electrode overlying said gate region; a dielectrically isolating layer on the pedestal sides except for localized regions thereof; and electrically contacting means to said source and drain through said localized regions.

Claim 19

An integrated circuit semiconductor device comprising: a fully dielectrically isolated semiconductor junction field effect transistor pedestal device; said pedestal including a bottom section of dielectrically isolating material, a top section of monocrystalline semiconductor material and a plurality of sides, said top section including a laterally central portion of a first conductivity type channel region of said transistor and a second conductivity type surface region of a second conductivity type, said central portion having side regions of said semiconductor material; said surface region of said top section being the gate region of said field effect transistor; source and drain regions of a second conductivity type located in a mutually opposing relationship in said side regions; a gate electrode overlying said gate region; a dielectrically isolating layer on the pedestal sides except for localized regions thereof; and electrically contacting means to said source and drain through said localized regions.

Claim 20

An integrated semiconductor structure comprising: a semiconductor body; a submicron-wide elongated protrusion having substantially vertical walls extending upwardly from and integral with said body, said protrusion including a bottom portion of a dielectric material fully dielectrically isolating said protrusion from said body and a top portion of monocrystalline semiconductor material, said top portion having a substantially horizontal top surface, said vertical walls having localized contact openings for establishing electrical contact with said top portion; said top portion including at least one semiconductor device; and electrical contacts established to at least said top surface.

Claim 21

An integrated semiconductor structure comprising: a semiconductor body; a submicron-wide elongated protrusion having substantially vertical walls extending upwardly from and integral with said body, said protrusion including a bottom portion of a dielectric material fully dielectrically isolating said protrusion from said body and a top portion of monocrystalline semiconductor material, said top portion having a substantially horizontal top surface, said vertical walls having localized contact openings for establishing electrical contact with said top portion; said top portion including at least one semiconductor device; and electrical contacts established to at least said top surface.

Claim 22

A free-standing semiconductor bipolar device structure comprising: a semiconductor body; a submicron-wide protrusion having substantially vertical walls extending from the integral with said body; said protrusion including a lower section of a dielectrically isolating material and an upper section of monocrystalline semiconductor material of a first conductivity type, said upper section including top and bottom portions, said bottom portion having a first width and said top portion having a second width smaller than said first width, said lower section dielectrically isolating said upper section from said body, and a laterally central portion of said upper section having said first width and coextensive with said top and bottom portions, said central portion being the first conductivity type base of said bipolar device; emitter and collector regions of a second conductivity type located in said bottom portion in a mutually opposing relationship with at least a portion of said base; insulator sidewalls of dissimilar thickness provided on said top and bottom portions, the thickness of said insulator sidewall on said top portion being larger than that on said bottom portion, said insulator sidewall on said bottom portion having openings exposing localized regions of said emitter and collector; and electrical contacts made to said localized regions.

Claim 23

A free-standing semiconductor bipolar device structure comprising: a semiconductor body; a submicron-wide protrusion having substantially vertical walls extending from the integral with said body; said protrusion including a lower section of a dielectrically isolating material and an upper section of monocrystalline semiconductor material of a first conductivity type, said upper section including top and bottom portions, said bottom portion having a first width and said top portion having a second width smaller than said first width, said lower section dielectrically isolating said upper section from said body, and a laterally central portion of said upper section having said first width and coextensive with said top and bottom portions, said central portion being the first conductivity type base of said bipolar device; emitter and collector regions of a second conductivity type located in said bottom portion in a mutually opposing relationship with at least a portion of said base; insulator sidewalls of dissimilar thickness provided on said top and bottom portions, the thickness of said insulator sidewall on said top portion being larger than that on said bottom portion, said insulator sidewall on said bottom portion having openings exposing localized regions of said emitter and collector; and electrical contacts made to said localized regions.