Patent US4757032A successfully refreshed from Google Patents.
US4757032A
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Method for DMOS semiconductor device fabrication
Assignee: STMicroelectronics SRL
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Filing: 1985-09-06
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Granted: 1988-07-12
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Expires: 2005-09-06
Abstract
Abstract An improved method for the fabrication of a DMOS transistor. The method comprises forming the source region of the transistor by introducing doping from a doped, thin polycrystalline layer. A thin insulating layer is used to protect the body channel contact region from the source doping, and the thin polycrystalline layer is completely consumed and converted into an insulator by oxidation subsequent to the source doping step.
Inventors
- 👤 Claudio Contiero
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:20
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
174 words
A method for the fabrication of a DMOS transistor in a semiconductor substrate, said DMOS transistor comprising a body channel region, a body channel contact region, a source region, a gate insulating layer, and a gate electrode, comprising the steps of: forming said body channel contact region in said semiconductor substrate; forming said gate insulating layer directly over the entirety of said body channel contact region; forming said gate electrode by patterning a layer of polycrystalline silicon deposited on said gate insulator; forming said channel body region; removing a portion of said gate insulating layer from said substrate including a portion of said channel body contact region; forming a thin layer of arsenic-doped polycrystalline silicon over said substrate, said thin layer of arsenic doped polycrystalline silicon being in contact with said body channel region and said body channel contact region; and diffusing from said thin layer of arsenic doped polycrystalline silicon to form said source region in said substrate where only said gate insulating layer masks said body contact region from said diffusing step.
Claim 2
Independent Claim
174 words
A method for the fabrication of a DMOS transistor in a semiconductor substrate, said DMOS transistor comprising a body channel region, a body channel contact region, a source region, a gate insulating layer, and a gate electrode, comprising the steps of: forming said body channel contact region in said semiconductor substrate; forming said gate insulating layer directly over the entirety of said body channel contact region; forming said gate electrode by patterning a layer of polycrystalline silicon deposited on said gate insulator; forming said channel body region; removing a portion of said gate insulating layer from said substrate including a portion of said channel body contact region; forming a thin layer of arsenic-doped polycrystalline silicon over said substrate, said thin layer of arsenic doped polycrystalline silicon being in contact with said body channel region and said body channel contact region; and diffusing from said thin layer of arsenic doped polycrystalline silicon to form said source region in said substrate where only said gate insulating layer masks said body contact region from said diffusing step.
Claim 3
Dependent Claim
15 words
The method according to claim 1, where the steps are performed in the order recited.
Claim 4
Dependent Claim
37 words
The method according to either claim 1 or claim 2, where said step of forming said thin layer of arsenic doped polycrystalline silicon includes forming a portion of said thin layer directly over said gate insulating layer.
Claim 5
Dependent Claim
53 words
The method according to either claim 1 or claim 2, further including the steps of completely oxidizing said thin layer of arsenic doped polycrystalline silicon to form an insulating and protective layer over said gate electrode, and then depositing electrically conductive material over said insulating and protective layer for contacting said source region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-12 | 1992-01-11 | 1992-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-12 | 1996-01-11 | 1996-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-12 | 2000-01-11 | 2000-07-12 | $7700.00 | Window Closed / Lapsed |