Patent US4755479A successfully refreshed from Google Patents.
US4755479A
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US
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Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers
Assignee: Fujitsu Ltd
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Filing: 1987-02-04
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Granted: 1988-07-05
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Expires: 2007-02-04
Abstract
Abstract With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve the problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this objective, the present invention discloses a method, in which reflowed sidewalls of doped silicate glass having a gentle slope are formed on both sides of a gate electrode, and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding a generation of the strong electric field and thus alleviates the short channel trouble. The present invention has also an effect of obtaining a passivation layer having gentle slope on the surface and avoiding a broken wire trouble of aluminum wiring.
Inventors
- 👤 Takao Miura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:31
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0229; H10D30/60; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/0147; H10P; H10P30/00; H10P30/20; H10P30/22; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/044; Y10S148/106; Y10S148/157; Y10S148/161; Y10S257/00; Y10S257/90; Y10S257/919; Y10S438/00; Y10S438/965
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
131 words
A method of manufacturing MIS FET, said method comprising the steps of: (a) forming a gate insulating film and a gate electrode on a silicon substrate; (b) depositing an insulating material on said substrate and said gate electrode; (c) reflowing said insulating material; (d) etching said reflowed insulating material until the surface of said gate electrode and substrate for source/drain regions are exposed, thereby making a gradually rising side wall of said reflowed insulating material remain on both sides of the gate electrode; and (e) implanting impurity ions into said substrate to form source/drain regions of said MIS FET using said gate electrode and said side walls as a mask, whereby a doping zone having a slanted profile which becomes gradually shallower under an edge of said gate electrode is formed.
Claim 2
Independent Claim
131 words
A method of manufacturing MIS FET, said method comprising the steps of: (a) forming a gate insulating film and a gate electrode on a silicon substrate; (b) depositing an insulating material on said substrate and said gate electrode; (c) reflowing said insulating material; (d) etching said reflowed insulating material until the surface of said gate electrode and substrate for source/drain regions are exposed, thereby making a gradually rising side wall of said reflowed insulating material remain on both sides of the gate electrode; and (e) implanting impurity ions into said substrate to form source/drain regions of said MIS FET using said gate electrode and said side walls as a mask, whereby a doping zone having a slanted profile which becomes gradually shallower under an edge of said gate electrode is formed.
Claim 3
Independent Claim
147 words
A method of manufacturing MIS FET, said method comprising the steps of: (a) forming a gate insulating film and a gate electrode on a silicon substrate; (b) depositing an insulating material on said substrate and said gate electrode; (c) etching said insulating material until the surface of said gate electrode and substrate for source/drain regions are exposed, thereby making a side wall of said insulating material remain on both sides of said gate electrode; (d) reflowing the remaining insulating material, whereby a gradually rising side wall of said insulating material are formed on both sides of the gate electrode; and (e) implanting impurity ions into said substrate to form source/drain regions of said MIS FET using said gate electrode and said side walls as a mask, whereby a doping zone having a slanted profile which gradually becomes shallower under an edge of said gate electrode is formed.
Claim 4
Independent Claim
147 words
A method of manufacturing MIS FET, said method comprising the steps of: (a) forming a gate insulating film and a gate electrode on a silicon substrate; (b) depositing an insulating material on said substrate and said gate electrode; (c) etching said insulating material until the surface of said gate electrode and substrate for source/drain regions are exposed, thereby making a side wall of said insulating material remain on both sides of said gate electrode; (d) reflowing the remaining insulating material, whereby a gradually rising side wall of said insulating material are formed on both sides of the gate electrode; and (e) implanting impurity ions into said substrate to form source/drain regions of said MIS FET using said gate electrode and said side walls as a mask, whereby a doping zone having a slanted profile which gradually becomes shallower under an edge of said gate electrode is formed.
Claim 5
Independent Claim
28 words
A method of manufacturing MIS FET according to claims 1 or 2, wherein said insulating material is a doped silicate glass having a reflow temperature below 1100° C.
Claim 6
Dependent Claim
32 words
A method of manufacturing MIS FET according to claim 3, wherein said silicate glass is doped with an oxide of phosphorus (P) or boron (B) or arsenic (As), or a combination thereof.
Claim 7
Dependent Claim
43 words
A method of manufacturing MIS FET according to claim 1, wherein said etching step is performed until the surface of said gate electrode is exposed and the surface edge thereof is partly removed, forming a continuous curved surface together with said side wall.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-05 | 1992-01-04 | 1992-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-05 | 1996-01-04 | 1996-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-05 | 2000-01-04 | 2000-07-05 | $7700.00 | Window Closed / Lapsed |