Patent US2372677A successfully refreshed from Google Patents.
Patent US4754172A successfully refreshed from Google Patents.
US4754172A
Expired / Lapsed
US
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STL low impedance buffer/driver
Assignee: Texas Instruments Inc
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Filing: 1986-12-16
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Granted: 1988-06-28
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Expires: 2006-12-16
Abstract
Abstract The disclosure relates to an STL bipolar buffer/driver circuit having a low output impedance for driving capacitive leads and the like wherein the output resistor of the prior art circuits is replaced by an NPN bipolar transistor and a further circuit including a series resistor, schottky diode and schottky clamp transistor for controlling the two output transistors.
Inventors
- 👤 Kevin M. Ovens
- 👤 Bobby D. Strong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/084; H03K19/0846
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
208 words
A circuit which comprises, in combination: (a) logic input means, (b) a voltage supply source, (c) a reference voltage source, (d) output means coupled across said supply source and said reference voltage source including a bipolar transistor having electron emitting, electron collecting and control electrodes and a schottky transistor having electron emitting, electron collecting and control electrodes, the electron collecting electrode of said bipolar transistor being coupled to said supply source and the electron emitting electrode of said bipolar transistor being coupled to the electron collecting electrode of said schottky transistor, the electron emitting electrode of said schottky transistor being coupled to said reference voltage source, and an output terminal coupled to the electron emitting electrode of said bipolar transistor, said input means being coupled to the control electrode of said schottky transistor, and (e) and a drive circuit responsive to said input means and coupled to the control electrode of said bipolar transistor for driving said bipolar transistor, said drive circuit including a second schottky transistor having electron emitting, electron collecting and control electrodes, the control electrode thereof being coupled to said input means and a schottky diode coupled between the electron collecting electrode of said second shottky diode and said control electrode of said bipolar transistor.
Claim 2
Dependent Claim
208 words
A circuit which comprises, in combination: (a) logic input means, (b) a voltage supply source, (c) a reference voltage source, (d) output means coupled across said supply source and said reference voltage source including a bipolar transistor having electron emitting, electron collecting and control electrodes and a schottky transistor having electron emitting, electron collecting and control electrodes, the electron collecting electrode of said bipolar transistor being coupled to said supply source and the electron emitting electrode of said bipolar transistor being coupled to the electron collecting electrode of said schottky transistor, the electron emitting electrode of said schottky transistor being coupled to said reference voltage source, and an output terminal coupled to the electron emitting electrode of said bipolar transistor, said input means being coupled to the control electrode of said schottky transistor, and (e) and a drive circuit responsive to said input means and coupled to the control electrode of said bipolar transistor for driving said bipolar transistor, said drive circuit including a second schottky transistor having electron emitting, electron collecting and control electrodes, the control electrode thereof being coupled to said input means and a schottky diode coupled between the electron collecting electrode of said second shottky diode and said control electrode of said bipolar transistor.
Claim 3
Dependent Claim
16 words
A circuit as set forth in claim 1 wherein said input means includes an AND circuit.
Claim 4
Dependent Claim
221 words
A circuit which comprises, in combination: (a) input means, (b) a voltage supply source, (c) a reference voltage source, (d) output means coupled across said supply source and said reference voltage source including a bipolar transistor and a first schottky transistor having a control electrode, an electron emitting electrode and an electron collecting electrode, said bipolar transistor having an electron collecting electrode coupled to said supply source and an electron emitting electrode coupled to the electron collecting electrode of said first schottky transistor being coupled to said reference voltage source, and an output terminal coupled to the electron emitting electrode of said bipolar transistor, said input means being coupled to the control electrode of said first schottky transistor, wherein said input means includes a series connected circuit comprising a second schottky transistor having an electron emitting electrode, an electron collecting electrode and a control electrode, a schottky diode having one electrode thereof coupled to the electron collecting electrode of said second schottky transistor, first resistance means coupled to said supply source and to the other electrode of said schottky diode and second resistance means coupled to said reference voltage source and to the electron emitting electrode of said second schottky transistor, the control electrode of said bipolar transistor being coupled to the junction of said diode and said first resistance means.
Claim 5
Dependent Claim
221 words
A circuit which comprises, in combination: (a) input means, (b) a voltage supply source, (c) a reference voltage source, (d) output means coupled across said supply source and said reference voltage source including a bipolar transistor and a first schottky transistor having a control electrode, an electron emitting electrode and an electron collecting electrode, said bipolar transistor having an electron collecting electrode coupled to said supply source and an electron emitting electrode coupled to the electron collecting electrode of said first schottky transistor being coupled to said reference voltage source, and an output terminal coupled to the electron emitting electrode of said bipolar transistor, said input means being coupled to the control electrode of said first schottky transistor, wherein said input means includes a series connected circuit comprising a second schottky transistor having an electron emitting electrode, an electron collecting electrode and a control electrode, a schottky diode having one electrode thereof coupled to the electron collecting electrode of said second schottky transistor, first resistance means coupled to said supply source and to the other electrode of said schottky diode and second resistance means coupled to said reference voltage source and to the electron emitting electrode of said second schottky transistor, the control electrode of said bipolar transistor being coupled to the junction of said diode and said first resistance means.
Claim 6
Dependent Claim
22 words
A circuit as set forth in claim 3 wherein the control electrodes of said first and second schottky transistors are connected together.
Claim 7
Dependent Claim
16 words
A circuit as set forth in claim 2 wherein said input means includes an AND circuit.
Claim 8
Dependent Claim
16 words
A circuit as set forth in claim 4 wherein said input means includes an AND circuit.
Claim 9
Dependent Claim
108 words
An STL circuit which includes, in combination: (a) input means for providing an input signal, said input means including a schottky diode serially connected to a second schottky transistor, said input signal driving said second schottky diode, (b) a voltage supply source, (c) a reference voltage source, and (d) output means coupled across said supply source and said reference voltage source including a low impedance bipolar transistor and a first schottky transistor serially connected thereto, and an output terminal coupled to the junctions of said bipolar transistor and said first schottky transistor, said input signal controlling said first schottky transistor and said schottky diode driving said bipolar transistor.
Claim 10
Dependent Claim
108 words
An STL circuit which includes, in combination: (a) input means for providing an input signal, said input means including a schottky diode serially connected to a second schottky transistor, said input signal driving said second schottky diode, (b) a voltage supply source, (c) a reference voltage source, and (d) output means coupled across said supply source and said reference voltage source including a low impedance bipolar transistor and a first schottky transistor serially connected thereto, and an output terminal coupled to the junctions of said bipolar transistor and said first schottky transistor, said input signal controlling said first schottky transistor and said schottky diode driving said bipolar transistor.
Claim 11
Dependent Claim
26 words
The circuit of claim 7 further including voltage swing reduction means coupled to the control electrode of said bipolar transistor to reduce the voltage swing thereof.
Claim 12
Dependent Claim
196 words
An STL circuit which includes, in combination: (a) input means for receiving an input signal, (b) a voltage supply source, (c) a reference voltage source, and (d) output means coupled across said supply source and said reference voltage source including a low impedance bipolar transistor and a first schottky transistor serially connected thereto having an electron emitting electrode, an electron collecting electrode and a control electrode, and an output terminal coupled to the junctions of said bipolar transistor and said first schottky transistor, said input signal controlling said first schottky transistor, wherein said voltage swing reduction means includes a series connected circuit comprising a second schottky transistor having an electron emitting electrode, an electron collecting electrode and a control electrode, a schottky diode having one electrode thereof coupled to the electron collecting electrode of said second schottky transistor, first resistance means coupled to said supply source and to the other electrode of said schottky diode and second resistance means coupled to said reference voltage source and to the electron emitting electrode of said second schottky transistor, the control electrode of said bipolar transistor being coupled to the junction of said diode and said first resistance means.
Claim 13
Dependent Claim
196 words
An STL circuit which includes, in combination: (a) input means for receiving an input signal, (b) a voltage supply source, (c) a reference voltage source, and (d) output means coupled across said supply source and said reference voltage source including a low impedance bipolar transistor and a first schottky transistor serially connected thereto having an electron emitting electrode, an electron collecting electrode and a control electrode, and an output terminal coupled to the junctions of said bipolar transistor and said first schottky transistor, said input signal controlling said first schottky transistor, wherein said voltage swing reduction means includes a series connected circuit comprising a second schottky transistor having an electron emitting electrode, an electron collecting electrode and a control electrode, a schottky diode having one electrode thereof coupled to the electron collecting electrode of said second schottky transistor, first resistance means coupled to said supply source and to the other electrode of said schottky diode and second resistance means coupled to said reference voltage source and to the electron emitting electrode of said second schottky transistor, the control electrode of said bipolar transistor being coupled to the junction of said diode and said first resistance means.
Claim 14
Dependent Claim
26 words
The circuit of claim 9 further including voltage swing reduction means coupled to the control electrode of said bipolar transistor to reduce the voltage swing thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-28 | 1991-12-28 | 1992-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-28 | 1995-12-28 | 1996-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-28 | 1999-12-28 | 2000-06-28 | $7700.00 | Window Closed / Lapsed |