US3867644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed low power schottky integrated logic gate circuit with current boost
Assignee: Signetics Corp
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Filing: 1974-01-07
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Granted: 1975-02-18
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Expires: 1994-01-07
Abstract
Abstract A high speed low power Schottky integrated logic gate circuit of a quadruple two input NAND gate type provides an adequate input voltage threshold even under increasing ambient temperatures by providing an additional transistor Vbe drop to the existing 2Vbe voltage drop circuit but yet maintains the high speed of the circuit by use of an additional current boosting transistor.
Inventors
- 👤 Ronald L Cline
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:50
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K17/00; H03K17/14
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
162 words
In a high speed low power Schottky integrated logic gate circuit having between input and common a 2Vbe transistor voltage drop produced by first and second cascaded Schottky transistors and an opposite diode voltage drop produced by diode means coupled to said input, said voltage drops determining the threshold input voltage level, VTH, at which switching occurs, an increase in ambient temperature tending to reduce said voltage drops and to reduce said VTH whereby said circuit is more susceptible to noise the improvement comprising: a third transistor coupled to said first transistor in a sense to add to said Vbe of said first transistor to raise said VTH, said third transistor having its control terminal coupled to said diode means; pull out resistor means connected to said first transistor for pulling out said first transistor, current boost transistor means connected between said third transistor and a d.c. voltage source for providing a low impedance high current path for charging associated parasitic capacitances.
Claim 2
Dependent Claim
162 words
In a high speed low power Schottky integrated logic gate circuit having between input and common a 2Vbe transistor voltage drop produced by first and second cascaded Schottky transistors and an opposite diode voltage drop produced by diode means coupled to said input, said voltage drops determining the threshold input voltage level, VTH, at which switching occurs, an increase in ambient temperature tending to reduce said voltage drops and to reduce said VTH whereby said circuit is more susceptible to noise the improvement comprising: a third transistor coupled to said first transistor in a sense to add to said Vbe of said first transistor to raise said VTH, said third transistor having its control terminal coupled to said diode means; pull out resistor means connected to said first transistor for pulling out said first transistor, current boost transistor means connected between said third transistor and a d.c. voltage source for providing a low impedance high current path for charging associated parasitic capacitances.
Claim 3
Dependent Claim
33 words
A circuit as in claim 1 where said first transistor has a base to emitter capacitance in part determined by said pull out resistor means said current boost transistor means charging such capacitance.
Claim 4
Dependent Claim
38 words
A circuit as in claim 1 where said third transistor is in a separate integrated circuit isolation tub from said input diode means anD said current boost transistor means pulls up such tub toward said d.c. voltage source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-17 | 1978-08-19 | 1979-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-17 | 1982-08-19 | 1983-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-17 | 1986-08-19 | 1987-02-18 | $7700.00 | Window Closed / Lapsed |