Switched capacitor finite impulse response filter

Claim 2

A symmetric finite impulse response filter characterized by a predetermined transfer function having a plurality of predetermined symmetric coefficient pairs, comprised of: (a) means for receiving an input signal, said input signal comprising a sequence of bits having predetermined logic levels; (b) a plurality of capacitors, having respective capacitances proportional to corresponding ones of said coefficient pairs, and with each capacitor of said plurality having its first terminal connected to the first terminals of each of the other said plurality of capacitors; (c) means for successively detecting the logic levels of said received bits and successively charging first predetermined ones of said capacitors to one of a positive or negative voltage via second terminals of said capacitors in the event individual bits of first predetermined pairs of said received bits corresponding to first predetermined ones of said corresponding coefficient pairs have the same logic level, and maintaining further ones of said capacitors discharged in the event individual bits of further predetermined pairs of said received bits corresponding to further predetermined ones of said corresponding coefficient pairs have opposite logic levels; and (d) means connected to said first terminals of said plurality of capacitors for successively summing the voltages of said capacitors and generating an output signal in response to said summing, whereby said output signal is an analog version of said digital input signal filtered according to said predetermined transfer function.

Claim 3

A symmetric finite impulse response filter as defined in claim 1 being of odd order and characterized by a transfer function having an additional coefficient, further including an additional capacitor having a capacitance approximately equal in value to said additional coefficient and said additional capacitor having a first terminal connected to said means for successively summing the voltages of said plurality of capacitors, and means for successively detecting the logic level of an additional bit of said sequence of bits corresponding to said additional coefficient and successively charging said additional capacitor to one of said positive or negative voltage in response to said logic level being detected.

Claim 4

A symmetric finite impulse response filter as defined in claim 2, wherein said means for receiving said input signal is comprised of a plurality of serially connected shift registers for storing and shifting successive ones of said bits.

Claim 5

A symmetric finite impulse response filter as defined in claim 2, further comprised of: (e) a reference voltage source, (f) a bias voltage source, (g) first switch means for connecting said first terminals of said capacitors alternately between said bias voltage source and said means for successively summing voltages of said capacitors, and (h) a plurality of second switch means connected to said means for detecting the logic levels of said received bits, for connecting individual ones of said second terminals of said capacitors alternately between said source of bias voltage and said source of reference voltage in phase with said first switch means in the event said first corresponding pairs of bits are of a first predetermined one of said logic levels, whereby said capacitors are charged to one of either said positive or negative voltage, and connecting said individual ones of said second terminals alternately between said source of bias voltage and said source of reference voltage in opposite phase to said first switch means in the event said first corresponding pairs of bits are of a second opposite one of said logic levels, whereby said capacitors are charged to an opposite one of said positive or negative voltage.

Claim 6

A symmetric finite impulse response filter as defined in claim 2, wherein said means for successively summing voltages on said capacitors is comprised of an integrator circuit having an input connected to said first terminals of said capacitors and having an output for carrying said output signal.

Claim 7

A symmetric finite impulse response filter as defined in claim 1, wherein said respective capacitances of said plurality of capacitors are approximately equal in value to twice the value of either of the coefficients of said corresponding coefficient pairs.

Claim 8

A symmetric finite impulse response filter as defined in claim 6, wherein said means for receiving said input signal is comprised of a plurality of serially connected shift registers for storing and shifting successive ones of said bits.

Claim 9

A symmetric finite impulse response filter as defined in claim 6, further comprised of: (e) a reference voltage source, (f) a bias voltage source, (g) first switch means for connecting said first terminals of said capacitors alternately between said bias voltage source and said means for successively summing voltages of said capacitors, and (h) a plurality of second switch means connected to said means for detecting the logic levels of said received bits, for connecting individual ones of said second terminals of said capacitors alternately between said source of bias voltage and said source of reference voltage in phase with said first switch means in the event said first corresponding pairs of bits are of a first predetermined one of said logic levels, whereby said capacitors are charged to one of either said positive or negative voltage, and connecting said individual ones of said second terminals alternately between said source of bias voltage and said source of reference voltage in opposite phase to said first switch means in the event said first corresponding pairs of bits are of a second opposite one of said logic levels, whereby said capacitors are charged to an opposite one of said positive or negative voltage.

Claim 10

A symmetric finite impulse response filter as defined in claim 6, wherein said means for successively summing voltages on said capacitors is comprised of an integrator circuit having an input connected to said first terminals of said capacitors and having an output for carrying said output signal.

Claim 11

A symmetric finite impulse response filter as defined in claim 1, wherein said means for receiving said input signal is comprised of a plurality of serially connected shift registers for storing and shifting successive ones of said bits.

Claim 12

A symmetric finite impulse response filter as defined in claim 1, further comprised of: (e) a reference voltage source, (f) a bias voltage source, (g) first switch means for connecting said first terminals of said capacitors alternately between said bias voltage source and said means for successively summing voltages of said capacitors, and (h) a plurality of second switch means connected to said means for detecting the logic levels of said received bits, for connecting individual ones of said second terminals of said capacitors alternately between said source of bias voltage and said source of reference voltage in phase with said first switch means in the event said first corresponding pairs of bits are of a first predetermined one of said logic levels, whereby said capacitors are charged to one of either said positive or negative voltage, and connecting said individual ones of said second terminals alternately between said source of bias voltage and said source of reference voltage in opposite phase to said first switch means in the event said first corresponding pairs of bits are of a second opposite one of said logic levels, whereby said capacitors are charged to an opposite one of said positive or negative voltage.

Claim 13

A symmetric finite impulse response filter as defined in claim 1, wherein said means for successively summing voltages on said capacitors is comprised of an integrator circuit having an input connected to said first terminals of said capacitors and having an output for carrying said output signal.

Claim 14

A symmetric finite impulse response filter characterized by a predetermined transfer function having a plurality of positive and negative coefficient pairs, comprised of: (a) a plurality of serially connected shift registers for receiving and storing an input sequence of bits, (b) a plurality of first and second digital processing circuits connected to first and second predetermined ones of said shift registers, for detecting logic levels of first and second predetermined pairs of said received bits corresponding to respective ones of said positive and negative coefficient pairs, and generating control signals in response to the logic levels detected, (c) a plurality of capacitors having respective capacitances proportional to corresponding ones of said coefficient pairs, and each of said capacitors having its first terminal connected to the first terminal of each of the other said plurality of capacitors, (d) a plurality of switch means connected to respective ones of said plurality of first and second digital processing circuits and second terminals of respective ones of said capacitors, for receiving said control signals, (i) charging first predetermined ones of said capacitors to a positive voltage in response to reception of a first predetermined one of said control signals, (ii) charging second predetermined ones of said capacitors to a negative voltage in response to reception of said second predetermined one of a control signals, and (iii) discharging further predetermined ones of said capacitors in response to reception of a third predetermined one of said control signals, and (e) integrator means connected in a circuit to said first terminals of the capacitors for receiving and summing the voltages on said capacitors and generating an analog output signal in response to said summing, whereby said charging and discharging of said capacitors filters said input sequence of bits according to said transfer function and said integrator means converts said filtered sequence of bits to analog form.

Claim 15

A symmetric finite impulse response filter characterized by a predetermined transfer function having a plurality of positive and negative coefficient pairs, comprised of: (a) a plurality of serially connected shift registers for receiving and storing an input sequence of bits, (b) a plurality of first and second digital processing circuits connected to first and second predetermined ones of said shift registers, for detecting logic levels of first and second predetermined pairs of said received bits corresponding to respective ones of said positive and negative coefficient pairs, and generating control signals in response to the logic levels detected, (c) a plurality of capacitors having respective capacitances proportional to corresponding ones of said coefficient pairs, and each of said capacitors having its first terminal connected to the first terminal of each of the other said plurality of capacitors, (d) a plurality of switch means connected to respective ones of said plurality of first and second digital processing circuits and second terminals of respective ones of said capacitors, for receiving said control signals, (i) charging first predetermined ones of said capacitors to a positive voltage in response to reception of a first predetermined one of said control signals, (ii) charging second predetermined ones of said capacitors to a negative voltage in response to reception of said second predetermined one of a control signals, and (iii) discharging further predetermined ones of said capacitors in response to reception of a third predetermined one of said control signals, and (e) integrator means connected in a circuit to said first terminals of the capacitors for receiving and summing the voltages on said capacitors and generating an analog output signal in response to said summing, whereby said charging and discharging of said capacitors filters said input sequence of bits according to said transfer function and said integrator means converts said filtered sequence of bits to analog form.

Claim 16

A symmetric finite impulse response filter as defined in claim 13 being of odd order and characterized by a transfer function having an additional coefficient, further including: (a) an additional shift register connected in series with said plurality of shift registers, for receiving and storing an additional bit of said sequence of bits, said additional bit having a predetermined logic level, (b) an additional digital processing circuit connected to said additional shift register, for detecting the logic level of said additional bit, and generating one of said first and second predetermined control signals in response to detecting said logic level, (c) an additional capacitor having a capacitance approximately equal in value to said additional coefficient, and said additional capacitor having a first terminal connected to said integrator means, and (d) additional switch means connected to said additional digital processing circuit and a second terminal of said additional capacitor, for receiving said control signals, (i) charging said additional capacitor to a positive voltage in response to reception of said first predetermined control signal, and (ii) charging said additional capacitor to a negative voltage in response to reception of said second predetermined control signal.

Claim 17

A symmetric finite impulse response filter as defined in claim 14, wherein said additional digital processing circuit is further comprised of: (a) a first logic circuit for generating said second predetermined control signal in response to detecting a logic low level of said additional bit, and (b) a second logic circuit for generating said first predetermined control signal in response to detecting a logic high level of said additional bit.

Claim 18

A symmetric finite impulse response filter as defined in claim 15, wherein said integrator circuit is comprised of an operational amplifier and a further capacitor connected to an input and output of the operational amplifier, said input being connected in a circuit to said first terminals of said plurality of capacitors.

Claim 19

A symmetric finite impulse response filter as defined in claim 15, further including an attenuating capacitor connected between said first terminal of said plurality of capacitors and said integrator means, for attenuating said voltages received by the integrator means.

Claim 20

A symmetric finite impulse response filter as defined in claim 13, wherein each of said plurality of first digital processing circuits is further comprised of: (a) a first logic circuit for generating said first predetermined control signal in response to detecting logic low levels of individual bits of a corresponding one of said predetermined pairs of received bits, (b) a second logic circuit for generating said second predetermined control signal in response to detecting logic high levels of said individual bits of the corresponding predetermined pair of received bits, and (c) a third logic circuit for generating said third predetermined control signal in response to detecting opposite logic levels of said individual bits of the corresponding predetermined pair of received bits.

Claim 21

A symmetric finite impulse response filter as defined in claim 18, wherein said integrator circuit is comprised of an operational amplifier and a further capacitor connected to an input and output of the operational amplifier, said input being connected in a circuit to said first terminals of said plurality of capacitors.

Claim 22

A symmetric finite impulse response filter as defined in claim 18, further including an attenuating capacitor connected between said first terminal of said plurality of capacitors and said integrator means, for attenuating said voltages received by the integrator means.

Claim 23

A symmetric finite impulse response filter as defined in claim 18, wherein said respective capacitances of said plurality of capacitors are approximately equal in value to twice the value of either of the coefficients of said corresponding coefficients pairs.

Claim 24

A symmetric finite impulse response filter as defined in claim 13, wherein each of said plurality of second digital processing circuits is further comprised of: (a) a first logic circuit for generating said second predetermined control signal in response to detecting logic low levels of individual bits of a corresponding one of said predetermined pairs of received bits, (b) a second logic circuit for generating said first predetermined control signal in response to detecting logic high levels of said individual bits of the corresponding predetermined pair of received bits, and (c) a third logic circuit for generating said third predetermined control signal in response to detecting opposite logic levels of said individual bits of the corresponding predetermined pair of received bits.

Claim 25

A symmetric finite impulse response filter as defined in claim 22, wherein said respective capacitances of said plurality of capacitors are approximately equal in value to twice the value of either of the coefficients of said corresponding coefficient pairs.

Claim 26

A symmetric finite impulse response filter as defined in claim 23, wherein sid integrator circuit is comprised of an operational amplifier and a further capacitor connected to an input and output of the operational amplifier, said input being connected in a circuit to said first terminals of said plurality of capacitors.

Claim 27

A symmetric finite impulse response filter as defined in claim 22, further including an attenuating capacitor connected between said first terminal of said plurality of capacitors and said integrator means, for attenuating said voltages received by the integrator means.

Claim 28

A symmetric finite impulse response filter as defined in claim 13, wherein said respective capacitances of said plurality of capacitors are approximately equal in value to twice the value of either of the coefficients of said corresponding coefficient pairs.

Claim 29

A symmetric finite impulse response filter as defined by claim 13, wherein said plurality of switch means are comprised of a plurality of transistor pairs, each of said transistor pairs having first terminals connected to the second terminals of said capacitors, and having second terminals connected to sources of positive and negative voltages respectively, and having control inputs connected to respective ones of said logic circuits.

Claim 30

A symmetric finite impulse response filter as defined in claim 27, wherein said first control signal is comprised of a pair of non-overlapping clock signals for application to respective control inputs of said transistor pairs, said second control signal is comprised of an opposite phase version of said pair of non-overlapping clock signals for application to said respective control inputs, and said third control signal is comprised of logical `1` and logical `0` voltages for application to said respective control inputs.