US4633425A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switched capacitor filter utilizing a differential input and output circuit
Assignee: Intel Corp
•
Filing: 1985-05-28
•
Granted: 1986-12-30
•
Expires: 2005-05-28
Abstract
Abstract An integrated circuit for filtering signals by having cascaded switched capacitor sampling filters. The circuit includes a transmit section which has an anti-aliasing filter, a core section filter, a highpass filter and an encoder for providing analog-to-digital conversion. Each successive filter is sampled at a lower rate to inhibit anti-aliasing. The circuit also includes a receive section which has a digital-to-analog decoder, an output buffer, a receiver core filter and a power amplifier.
Inventors
- 👤 Daniel Senderowicz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:36
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/005; H03H; H03H19/00; H03H19/004; H03F2200/00; H03F2200/372
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
95 words
An integrated circuit for filtering signals by having cascaded switched capacitor differential sampling filters comprising: transmit means for converting an analog input signal to a digital transmit signal, said transmit means comprises; (a) an anti-aliasing filter coupled to said analog input and providing an oversampled filtering; (b) a transmit core filter coupled to said anti-aliasing filter; (c) a highpass filter coupled to said transmit core filter; (d) an encoder coupled to said highpass filter and having a balanced differential input for generating said digital transmit signal; whereby power supply rejection and signal-to-noise ratios are improved.
Claim 2
Dependent Claim
95 words
An integrated circuit for filtering signals by having cascaded switched capacitor differential sampling filters comprising: transmit means for converting an analog input signal to a digital transmit signal, said transmit means comprises; (a) an anti-aliasing filter coupled to said analog input and providing an oversampled filtering; (b) a transmit core filter coupled to said anti-aliasing filter; (c) a highpass filter coupled to said transmit core filter; (d) an encoder coupled to said highpass filter and having a balanced differential input for generating said digital transmit signal; whereby power supply rejection and signal-to-noise ratios are improved.
Claim 3
Dependent Claim
41 words
The circuit of claim 1 wherein: anti-aliasing filter is a third-order elliptic filter and further including and preceded by a passive filter section; said transmit core filter is a fifth-order elliptic filter; said highpass filter further including an autozero correction circuit.
Claim 4
Dependent Claim
85 words
The circuit of claim 2 wherein said anti-aliasing filter is over sampled at a first rate, said transmit core filter is sampled at a second rate, and said highpass filter at a third rate, said first rate being at a frequency greater than a cutoff frequency of said passive filter section, said second rate being at a frequency greater than a cutoff frequency of said anti-aliasing filter, and said third rate being at a frequency greater than a cutoff frequency of said transmit core filter.
Claim 5
Dependent Claim
27 words
The circuit of claim 3 wherein said first rate is 1.024 MHz, said second rate is 128 KHz and said third rate is 8 KH z .
Claim 6
Dependent Claim
43 words
The circuit of claim 1 wherein said receive side comprises: a digital-to-analog decoder; a decoder output buffer coupled to said digital-to-analog decoder; a fifth order elliptic receive core filter coupled to said buffer; and a power amplifier coupled to said receive core filter.
References Cited (Backward Citations)
US4096576A
Cited
US4125900A
Cited
US4179665A
Cited
US4285045A
Cited
US4333064A
Cited
US4491712A
Cited
US4437075A
Cited
US4359778A
Cited
US4520283A
Cited
US4574250A
Cited
US4470126A
Cited
US4498063A
Cited
US4554633A
Cited
US4535474A
Cited
US4531106A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |