Switched-capacitor filter

Claim 2

A prefilter for the input stage of a switched-capacitor filter, said switched-capacitor filter comprising a switched capacitor and associated switching means common to said switched-capacitor filter and said prefilter, and being driven by primary clock pulses having a period T for sampling an input signal to be supplied to said switched-capacitor filter via said prefilter, wherein said prefilter comprises: (2 k -1) (k being a positive integer) units of switched capacitors; means for providing secondary clock pulse groups to drive said (2 k -1) units of switched capacitors, each of said secondary clock pulse groups having the same period T and the phases of said secondary clock pulse groups being shifted by T/2 k , 2T/2 k , 3T/2 k . . . (2 k -1)T/2 k with respect to said primary clock pulses; said switched capacitor common to said switched-capacitor filter and said prefilter being driven by said primary clock pulses; wherein each of said (2 k -1) units of switched capacitors samples and holds the input signal at each corresponding one of said secondary clock pulse groups successively, then, the signals sampled and held by said (2 k -1) switched capacitors are added to the signal sampled and held by said switched capacitor common to said switched-capacitor filter and said prefilter, and the sum signals are supplied to said switched-capacitor filter synchronously with said primary clock pulses.

Claim 3

A prefilter as set forth in claim 1, wherein the first through last sampled and held signals in said (2 k -1) units of switched capacitors are delayed successively by times T/2 k , 2T/2 k , 3T/2 k , . . . (2 k -1) T/2 k , respectively, and are added to said sampled and held signal in said switched capacitor common to said switched-capacitor filter.

Claim 4

A prefilter as set forth in claim 1, wherein said signals sampled and held first through last in said 2 k units of switched capacitors are stored temporarily and are then discharged simultaneously when the sampled and held signal in said switched capacitor common to said switched-capacitor filter is discharged.

Claim 5

A prefilter as set forth in claim 3, wherein all said switched capacitors are connected in parallel with each other.

Claim 6

A prefilter as set forth in claim 4, wherein each said switched capacitor comprises a capacitor, two terminals, and switching means for selectively connecting said capacitor to one or the other of said two terminals.

Claim 7

A prefilter as set forth in claim 5, wherein each said switching means comprises two FETs, one of said FETs operating to charge said capacitor of each said switched capacitor, and another of said FETs operating to discharge said capacitor of each said switched capacitor.

Claim 8

A prefilter as set forth in claim 6, wherein said respective FETs for charging said switched capacitors are made conductive sequentially, but said respective FETs for discharging said switched capacitors are made conductive simultaneously at a time which is synchronous with said primary clock pulses.

Claim 9

A prefilter for the input stage of a switched-capacitor filter, comprising: a first switched capacitor and a second switched capacitor, both connected in series, and a third switched capacitor, common to the switched-capacitor filter, connected in parallel with said series connected first and second switched capacitors, each said switched capacitor comprising two terminals, a capacitor, and switching means for selectively connecting said capacitor to one or the other of said two terminals; and said switching means of said second switched capacitor operating in phase with said switching means of said third switched capacitor and said switching means of said first switched capacitor operating in opposite phase with respect to said switching means of said third switched capacitor.

Claim 10

A prefilter for the input stage of a switched-capacitor filter, comprising: a first switched capacitor and a second switched capacitor, both connected in series, and a third switched capacitor, common to the switched-capacitor filter, connected in parallel with said series connected first and second switched capacitors, each said switched capacitor comprising two terminals, a capacitor, and switching means for selectively connecting said capacitor to one or the other of said two terminals; and said switching means of said second switched capacitor operating in phase with said switching means of said third switched capacitor and said switching means of said first switched capacitor operating in opposite phase with respect to said switching means of said third switched capacitor.

Claim 11

A prefilter as set forth in claim 8, wherein each said switching means comprises two FETs (field effect transistors), one of said FETs operating to charge said capacitor of each said switched capacitor, while another of said FETs operates to discharge said capacitor of each said switched capacitor.

Claim 12

A prefilter as set forth in claim 8 or claim 9, wherein the capacitance of said third switched capacitor is approximately one-half that of said second switched capacitor, and wherein the capacitance of said second switched capacitor is approximately equal to that of said first switched capacitor.

Claim 13

A prefilter driven by first and second clock signals, said prefilter comprising: an input signal; first and second means for supplying said first and second clock signals, respectively; a first transistor having a first terminal connected to said input terminal, a gate connected to said second clock supplying means, and a second terminal; a first capacitor having one terminal thereof connected to said second terminal of said first transistor and having the other terminal thereof connected to ground; a second transistor having a first terminal connected to said second terminal of said first transistor, a gate connected to said first clock supplying means, and a second terminal; a second capacitor having one terminal thereof connected to said second terminal of said second transistor and having the other terminal thereof connected to ground; a third transistor having a first terminal connected to said second terminal of said second transistor, a gate connected to the second clock supplying means, and a second terminal; a fourth transistor having a first terminal connected to said input terminal, a gate connected to the first clock supplying means, and a second terminal; a third capacitor having one terminal thereof connected to said second terminal of said fourth transistor and having the other terminal thereof connected to ground; a fifth transistor having a first terminal connected to said second terminal of said fourth transistor, a gate connected to the second clock supplying means, and a second terminal; and an output terminal connected to said second terminal of said fifth transistor and to said second terminal of said third transistor.

Claim 14

A prefilter driven by first and second clock signals, said prefilter comprising: an input signal; first and second means for supplying said first and second clock signals, respectively; a first transistor having a first terminal connected to said input terminal, a gate connected to said second clock supplying means, and a second terminal; a first capacitor having one terminal thereof connected to said second terminal of said first transistor and having the other terminal thereof connected to ground; a second transistor having a first terminal connected to said second terminal of said first transistor, a gate connected to said first clock supplying means, and a second terminal; a second capacitor having one terminal thereof connected to said second terminal of said second transistor and having the other terminal thereof connected to ground; a third transistor having a first terminal connected to said second terminal of said second transistor, a gate connected to the second clock supplying means, and a second terminal; a fourth transistor having a first terminal connected to said input terminal, a gate connected to the first clock supplying means, and a second terminal; a third capacitor having one terminal thereof connected to said second terminal of said fourth transistor and having the other terminal thereof connected to ground; a fifth transistor having a first terminal connected to said second terminal of said fourth transistor, a gate connected to the second clock supplying means, and a second terminal; and an output terminal connected to said second terminal of said fifth transistor and to said second terminal of said third transistor.

Claim 15

The prefilter of claim 11, wherein the capacitance of said first capacitor is approximately twice that of said third first capacitor, and wherein the capacitance of said second capacitor is approximately twice that of said third capacitor.