Signal shaping circuit

Claim 2

A signal shaping circuit comprising means for receiving samples of an input signal in periodically recurring time intervals, first and second storing means, coupling means having an input connected to said first storing means and an output, first means for applying the signal in said first storing means to said second storing means through said coupling means during a first portion of said time interval, second means for separately applying a sample of said input signal from said receiving means to said first storing means during said first portion, and third means operative during the remainder of said time interval for interconnecting said first and second storing means to combine the signal sample in said first storing means with the coupled signal previously applied to said second storing means whereby the signal at said coupling means output is modified in a predetermined manner with respect to said input signal.

Claim 3

A shaping circuit according to claim 1 wherein each of said first and second storing means comprises a storage capacitor and said coupling means comprises amplifying means.

Claim 4

A signal shaping circuit according to claim 2 wherein said first means comprises switching means for connecting the output of said amplifying means to said second storage capacitor during one part of said time interval first portion, said second means comprises switching means for connecting said receiving means to said first storage capacitor during a succeeding part of said time interval first portion, and said third means comprises switching means for connecting said first storage capacitor to said second storage capacitor during the remainder of said time interval.

Claim 5

A signal equalizer circuit comprising means for receiving a sample of an input signal during a selected time slot of a group of periodically recurring time slots, first and second storage capacitors, amplifying means having an input connected to said first storage capacitor and an output, means for generating first, second and third successively occurring periodic control signals, first, second and third switches each having a first, a second and a control electrode, said first switching means having its first electrode connected to said amplifying means output and its second electrode connected to said second storage capacitor and being responsive to said first occurring control signal applied to its control electrode to connect said amplifying means output to said second storage capacitor, said second switch having its first electrode connected to said receiving means and its second electrode connected to said first storage capacitor and being responsive to said second occurring control signal for connecting said receiving means to said first storage capacitor, and said third switch having its first electrode connected to said first storage capacitor and its second electrode connected to said second storage capacitor and being responsive to said third occurring control signal for connecting said first storage capacitor to said second storage capacitor whereby the signal at said amplifying means output is modified in a predetermined manner with respect to said input signal.

Claim 6

A signal equalizer circuit comprising means for receiving a sample of an input signal during a selected time slot of a group of periodically recurring time slots, first and second storage capacitors, amplifying means having an input connected to said first storage capacitor and an output, means for generating first, second and third successively occurring periodic control signals, first, second and third switches each having a first, a second and a control electrode, said first switching means having its first electrode connected to said amplifying means output and its second electrode connected to said second storage capacitor and being responsive to said first occurring control signal applied to its control electrode to connect said amplifying means output to said second storage capacitor, said second switch having its first electrode connected to said receiving means and its second electrode connected to said first storage capacitor and being responsive to said second occurring control signal for connecting said receiving means to said first storage capacitor, and said third switch having its first electrode connected to said first storage capacitor and its second electrode connected to said second storage capacitor and being responsive to said third occurring control signal for connecting said first storage capacitor to said second storage capacitor whereby the signal at said amplifying means output is modified in a predetermined manner with respect to said input signal.

Claim 7

A signal equalizer circuit according to claim 4 wherein the ratio of said first storage capacitor to said second storage capacitor is a predetermined number and said amplifying means comprises an inverting amplifier.

Claim 8

A signal equalizer circuit according to claim 5 wherein said predetermined number is m > 2 and the gain of said inverting amplifier is m+1/m-1.

Claim 9

A signal equalizer circuit according to claim 6 wherein each of said first, second and third switches comprises an insulated gate field effect transistor having a gate, a source and a drain, said gate corresponding to said switch control electrode, saiD drain corresponding to said switch first electrode and said source corresponding to said switch second electrode.

Claim 10

A signal equalizer circuit according to claim 7 wherein said inverting amplifier comprises an IGFET having a gate, a source and a drain, said gate being the amplifier input, said drain being the amplifier output and said source being connected to a reference potential.

Claim 11

A signal shaping circuit comprising means for receiving samples of an input signal in periodically occurring time intervals, first, second and third stores, coupling means having an input connected to said second store and an output, means for generating first and second successively occurring control signals in each time interval, first means connected between said receiving means and said first store responsive to said first control signal for applying a sample of said input signal to said first store, second means connected between said coupling means output and said third store responsive to said first control signal for applying the signal obtained from said second store to said third store, third means connected between said first and second stores responsive to said second control signal for interconnecting said first and second stores, and fourth means connected between said second and third stores responsive to said second control signal for interconnecting said first and second stores with said third store to combine the signals in said first and second stores with the coupled signal previously applied to said third store whereby the signal at said coupling means output is modified in a predetermined manner with respect to said input signal.

Claim 12

A signal shaping circuit comprising means for receiving samples of an input signal in periodically occurring time intervals, first, second and third stores, coupling means having an input connected to said second store and an output, means for generating first and second successively occurring control signals in each time interval, first means connected between said receiving means and said first store responsive to said first control signal for applying a sample of said input signal to said first store, second means connected between said coupling means output and said third store responsive to said first control signal for applying the signal obtained from said second store to said third store, third means connected between said first and second stores responsive to said second control signal for interconnecting said first and second stores, and fourth means connected between said second and third stores responsive to said second control signal for interconnecting said first and second stores with said third store to combine the signals in said first and second stores with the coupled signal previously applied to said third store whereby the signal at said coupling means output is modified in a predetermined manner with respect to said input signal.

Claim 13

A shaping circuit according to claim 9 wherein each of said first, second and third stores comprises a storage capacitor and said coupling means comprises amplifying means.

Claim 14

A signal shaping circuit according to claim 10 wherein each of said first, second, third and fourth means comprises switching means, and said control signal generating means comprising means for generating a short first control signal at the beginning of each time interval and means for generating said second control signal for the remainder of the time interval.

Claim 15

A signal equalizer circuit comprising means for receiving a sample of an input signal during a selected time slot of a group of periodically recurring time slots, first, second and third storage capacitors, amplifying means having an input connected to said second storage capacitor and an output, means for generating first and second successively occurring periodic control signals, first, second, third and fourth switches each having first, second and control electrodes, said first switch having its first electrode connected to said signal receiving means and its second electrode connected to said first storage capacitor and being responsive to said first control signal applied to its control electrode for connecting said receiving means to said first storage capacitor, said second switch having its first electrode connected to said amplifing means output and its second electrode connected to said third storage capacitor and being responsive to said first control signal applied to its control electrode for connecting said amplifying means output to said third storage capacitor, said third switch having its first electrode connected to said first storage capacitor and its second electrode connected to said second storage capacitor and being responsive to said second control signal applied to its control electrode for interconnecting said first and second storage capacitors, and said fourth switch having its first electrode connected to said third storage capacitor and its second electrode connected to said storage capacitor and being responsive to the second control signal applied to its control electrode for interconnecting said second and third storage capacitors whereby the signal at said amplifying means output is modified in a predetermined manner with respect to said input signal.

Claim 16

A signal equalizer circuit comprising means for receiving a sample of an input signal during a selected time slot of a group of periodically recurring time slots, first, second and third storage capacitors, amplifying means having an input connected to said second storage capacitor and an output, means for generating first and second successively occurring periodic control signals, first, second, third and fourth switches each having first, second and control electrodes, said first switch having its first electrode connected to said signal receiving means and its second electrode connected to said first storage capacitor and being responsive to said first control signal applied to its control electrode for connecting said receiving means to said first storage capacitor, said second switch having its first electrode connected to said amplifing means output and its second electrode connected to said third storage capacitor and being responsive to said first control signal applied to its control electrode for connecting said amplifying means output to said third storage capacitor, said third switch having its first electrode connected to said first storage capacitor and its second electrode connected to said second storage capacitor and being responsive to said second control signal applied to its control electrode for interconnecting said first and second storage capacitors, and said fourth switch having its first electrode connected to said third storage capacitor and its second electrode connected to said storage capacitor and being responsive to the second control signal applied to its control electrode for interconnecting said second and third storage capacitors whereby the signal at said amplifying means output is modified in a predetermined manner with respect to said input signal.

Claim 17

A signal equalizer circuit according to claim 12 wherein said second storage capacitor is much smaller than said first storage capacitor, the ratio of the sum of said first and second storage capacitors to said third storage capacitor is a predetermined number and said amplifying means comprises an inverting amplifier.

Claim 18

A signal equalizer circuit according to claim 13 wherein said predetermined number is m > 2 and the gain of said inverting amplifier is m+1/m-1.

Claim 19

A signal equalizer circuit according to claim 14 wherein each of said first, second, third and fourth switches comprises an IGFET having a gate, a source and a drain, said gate corresponding to said switch control electrode, said drain corresponding to said switch first electrode and said source corresponding to said switch second electrode.

Claim 20

A signal equalizer circuit according to claim 15 wherein said inverting amplifier comprises an IGFET having a gate, a drain and a source, said gate being the amplifier input, said drain being the amplifier output and said source being connected to a reference potential.

Claim 21

In a time division communication system wherein a plurality of time slots occurs in repetitive frames and having means for receiving a sample of an input signal in a selected time slot, a filter circuit comprising first, second and third storage capacitors, amplifying means having an input connected to said second storage capacitor and an output, apparatus operative during said selected time slot comprising first means for applying said input signal sample to said first storage capacitor and second means for applying the amplified contents of said second storage capacitor to said third storage capacitor, and apparatus operative between successive occurrences of said selected time slot comprising means for interconnecting said first and second storage capacitors and means for interconnecting said second and third storage capacitors to redistribute charge between said first and second capacitors and said third capacitor whereby the signal at the amplifying means output is modified in a predetermined manner with respect to said input signal.

Claim 22

In a time division communication system wherein a plurality of time slots occurs in repetitive frames and having means for receiving a sample of an input signal in a selected time slot, a filter circuit comprising first, second and third storage capacitors, amplifying means having an input connected to said second storage capacitor and an output, apparatus operative during said selected time slot comprising first means for applying said input signal sample to said first storage capacitor and second means for applying the amplified contents of said second storage capacitor to said third storage capacitor, and apparatus operative between successive occurrences of said selected time slot comprising means for interconnecting said first and second storage capacitors and means for interconnecting said second and third storage capacitors to redistribute charge between said first and second capacitors and said third capacitor whereby the signal at the amplifying means output is modified in a predetermined manner with respect to said input signal.

Claim 23

In a time division communication system wherein a plurality of time slots occurs in repetitive frames and having means for receiving a sample of an input signal in a selected time slot, a filter circuit according to claim 17 wherein said first means comprises a switch connected between said signal receiving means and said first storage capacitor, said second means comprises a switch connected between said amplifying means output and said third storage capacitor, said third means comprises a switch connected between said first and second storage capacitors, said fourth means comprises a switch connected between said second and third storage capacitors, and said amplifying means comprises an inverting amplifier.

Claim 24

In a time division communication system wherein a plurality of time slots occurs in repetitive frames and having means for receiving a sample of an input signal in a selected time slot, a filter circuit according to claim 18 wherein said second storage capacitor is much smaller than said first storage capacitor, the ratio of the sum of said first and second storage capacitors to said third storage capacitor is a predetermined number m > 2 and the gain of said amplifier is m+1/m-1.

Claim 25

In a signal transmission system having a zero order hold sampling arrangement, a signal equalizer circuit comprising means for periodically sampling the output of said zero order hold arrangement, first and second capacitors, an inverting amplifier having an input connected to said first capacitor and an output, means operative just prior to the sampling of said zero order hold arrangement for applying a signal corresponding to the signal stored in said first capacitor from said amplifier output to said second storage capacitor, means operative during said sampling for applying the Sample from the zero order holding arrangement to said first capacitor, and means operative just after said sampling for interconnecting said first and second storage capacitors to redistribute charge therebetween whereby said amplifier output signal is modified in a predetermined manner with respect to said sample input.

Claim 26

In a signal transmission system having a zero order hold sampling arrangement, a signal equalizer circuit comprising means for periodically sampling the output of said zero order hold arrangement, first and second capacitors, an inverting amplifier having an input connected to said first capacitor and an output, means operative just prior to the sampling of said zero order hold arrangement for applying a signal corresponding to the signal stored in said first capacitor from said amplifier output to said second storage capacitor, means operative during said sampling for applying the Sample from the zero order holding arrangement to said first capacitor, and means operative just after said sampling for interconnecting said first and second storage capacitors to redistribute charge therebetween whereby said amplifier output signal is modified in a predetermined manner with respect to said sample input.

Claim 27

A signal shaping circuit comprising means for periodically sampling an input signal, first and second storing means, coupling means having an input connected to said first storing means and an output, first means for applying the contents of said first storing means to said second storing means via said coupling means, second means for applying the sample of said input signal to said first storing means, and third means for combining the sampled signal in said first storing means with the contents of said second storing means whereby the output of said coupling means is modified in a predetermined manner with respect to said sampled input signal.

Claim 28

A signal shaping circuit comprising means for periodically sampling an input signal, first and second storing means, coupling means having an input connected to said first storing means and an output, first means for applying the contents of said first storing means to said second storing means via said coupling means, second means for applying the sample of said input signal to said first storing means, and third means for combining the sampled signal in said first storing means with the contents of said second storing means whereby the output of said coupling means is modified in a predetermined manner with respect to said sampled input signal.

Claim 29

A signal shaping circuit according to claim 21 wherein each of said first and second storing means comprises a storage capacitor and said third means comprises means for redistributing the charge in said first storage capacitor corresponding to said sampled signal with the charge in said second storage capacitor.