Parallel programmable charge domain device

Claim 1

A parallel programmable charge domain device for multiplying a sampled analog signal represented by a quantity of stored charge by a multiple bit digital word coefficient comprising: a semiconductor substrate having electrodes insulatively disposed thereon to which signal potentials are applied for inducing wells in said substrate for the storage and propagation of packets of charge therein; an input signal charge storage well formed in said substrate; means for introducing a charge packet in said input signal charge storage well having a magnitude corresponding to the value of an applied analog signal; a plurality of charge splitter wells formed in said substrate; means for simultaneously distributing substantially the entire charge packet in said input signal charge storage well among said plurality of charge splitter wells; individual ones of said plurality of charge splitter wells except the last one of said plurality of charge splitter wells receiving a 1/2 N fractional portion of the charge packet in said input signal charge storage well, where N is an integer denoting the ordered number of an individual one of said plurality of charge splitter wells; said last one of said plurality of charge splitter wells receiving the same fractional portion of the charge packet in said input signal charge storage well as the penultimate one of said plurality of charge splitter wells; a first and a second charge accumulator well formed in said substrate; first charge transfer gating means associated with individual ones of said plurality of charge splitter wells for selectively enabling the transfer of the charge packets stored therein to said first charge accumulator well; second charge transfer gating means associated with individual ones of said plurality of charge splitter wells for selectively enabling the transfer of the charge packets stored therein to said second charge accumulator well; means for applying the ordered bits of a multiple bit digital word to said first charge transfer gating means starting with the application of the most significant bit of said digital word to the lowest ordered individual one of said plurality of charge storage wells, a bit of one value enabling the transfer of the charge packet in the associated individual one of said plurality of charge splitter wells to said first charge accumulator well; means for applying the complementary ones of said ordered bits of said multiple bit digital word to said second charge transfer gating means starting with the application of the most significant complementary bit of said digital word to the lowest ordered individual one of said plurality of charge storage wells, a complementary bit of said one value enabling the transfer of the charge packet in the associated individual one of said plurality of charge splitter wells to said second charge accumulator well; and charge combiner means coupled to said first and said second charge accumulator wells for providing an output signal whose value corresponds to the difference in the magnitudes of the charge packets stored in said first and said second charge accumulator wells.