Charge-coupled multiplying digital-to-analog converter

Claim 1

A multiplying digital-to-analog converter comprising: a substrate, capable of being implemented with charge-coupled devices (CCDs) on its surface; a first plurality of N means, disposed on the surface of the substrate, for receiving a digital word b 1 b 2 b 3 . . . b N , where N is the word length, each means receiving only one of the digits b i , 1≦i≦N; a second plurality of N means, implemented on the substrate as potential wells X i , for receiving a positive charge Q S +Q B , which results from the addition of a bipolar signal voltage S to a voltage bias B, B≦|S|; a third plurality of N means, implemented on the substrate as potential wells Y i in apposition to the potential wells X i , for receiving a positive charge -Q S +Q B , which results from the subtraction of the signal voltage S from the voltage bias B; a fourth plurality of N means, implemented on the substrate between the potential wells X i and Y i , for gating equilibrated charges which are in apposition, equilibration occurring only if the digit b i equals 0; a fifth plurality of N pairs of means, implemented upon the substrate and having channel stops diffused into them, for receiving the equilibrated charges, the charge on one portion of each of the N pairs of wells being dumped to ground; and a sixth means implemented on the substrate as a larger potential well, which accepts the undumped charges from the fifth means, the means for receiving the equilibrated charges, for forming a product having the factors Q S and the two's complement number b N b N-1 . . . b 2 b 1 .