US4661948A
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Digital quadrature amplitude modulator
Assignee: Fairchild Semiconductor Corp
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Filing: 1985-02-12
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Granted: 1987-04-28
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Expires: 2005-02-12
Abstract
Abstract In a quadrature amplitude modulator, two binary, synchronous data signals representing four possible phase states of a carrier signal are sampled and respectively fed into two shift registers comprising part of a finite impulse response lowpass filter. The samples in each corresponding pair of stages in the shift registers are multiplexed at twice the carrier frequency. Each multiplexer output is then added modulo-two to a binary signal at the carrier frequency using exclusive-OR gates. The gate outputs are weighted in a desired fashion and summed and converted to an analog signal which exhibits a preferred spectral shape. This approach enables the quadrature amplitude modulation function to be included within the structure of the finite impulse response lowpass filter. The binary synchronous nature of the input data enables the structure of the filter to be simplified and the number of multiplexers and modulo-two adders to be reduced to a number equal to the number of bits stored from the input sequences. An extension of this basic concept includes higher levels of encoding, specifically the case of sixteen or more possible phase and amplitude states of a carrier signal. The particular method for weighting and summing the multiplexed and modulated signals may utilize digital logic combined with resistors, switched capacitors, or a stored program combined with a digital-to-analog converter, and is suitable for integrated circuit fabrication.
Inventors
- 👤 Garry R. Shapiro
- 👤 Charles S. Meyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:21
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/32; H04L27/34; H04L27/36; H04L27/365
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
95 words
A method for quadrature amplitude modulation of a carrier signal with plural binary synchronous sequences, comprising the steps of: storing at least one bit of each of the binary synchronous sequences; multiplexing the stored bits at a frequency that is an integer multiple of the frequency of the carrier signal to produce a multiplexed multibit signal; modulating a square wave signal having a frequency equal to that of the carrier frequency of the quadrature amplitude modulation with the multiplexed multibit signal; and spectrally shaping the modulated square wave signal to generate a quadrature-amplitude-modulated analog signal.
Claim 2
Independent Claim
95 words
A method for quadrature amplitude modulation of a carrier signal with plural binary synchronous sequences, comprising the steps of: storing at least one bit of each of the binary synchronous sequences; multiplexing the stored bits at a frequency that is an integer multiple of the frequency of the carrier signal to produce a multiplexed multibit signal; modulating a square wave signal having a frequency equal to that of the carrier frequency of the quadrature amplitude modulation with the multiplexed multibit signal; and spectrally shaping the modulated square wave signal to generate a quadrature-amplitude-modulated analog signal.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein said step of modulating the square wave signal comprises modulo-2 addition of the square wave signal and the multiplexed multibit signal.
Claim 4
Dependent Claim
55 words
The method of claim 1 wherein plural successive bits of each of said binary synchronous sequences are simultaneously stored and multiplexed to produce plural multiplexed multibit signals, and wherein said plural multiplexed signals are simultaneously modulated with said square wave signal to produce plural modulated signals that are filtered to generate said modulated analog signal.
Claim 5
Dependent Claim
53 words
The method of claim 3 wherein said filtering step comprises the steps of taking multiple samples of each modulated signal during each cycle of said square wave signal, weighting each sample in accordance with a desired output spectrum, and summing the weighted sample from each modulated signal to generate said modulated analog signal.
Claim 6
Dependent Claim
23 words
The method of claim 1 wherein said stored bits are multiplexed at a freqeuency that is twice the frequency of the carrier signal.
Claim 7
Dependent Claim
113 words
A modulator for generating a quadrature phase-shift keyed signal from two binary synchronous sequences, comprising: means for storing data elements of each of the two binary synchronous sequences; a multiplexer unit for switching between the stored elements of each of the two sequences at a frequency equal to twice a predetermined carrier frequency to produce multiplexed signals representative of successive data symbols; means for logically combining the multiplexed signals with a square wave signal having a frequency equal to said carrier frequency of the quadrature phase-shift keyed signal; and means for generating a spectrally shaped sinusoidal signal in response to the signals produced from the combinations of said multiplexed and square wave signals.
Claim 8
Dependent Claim
113 words
A modulator for generating a quadrature phase-shift keyed signal from two binary synchronous sequences, comprising: means for storing data elements of each of the two binary synchronous sequences; a multiplexer unit for switching between the stored elements of each of the two sequences at a frequency equal to twice a predetermined carrier frequency to produce multiplexed signals representative of successive data symbols; means for logically combining the multiplexed signals with a square wave signal having a frequency equal to said carrier frequency of the quadrature phase-shift keyed signal; and means for generating a spectrally shaped sinusoidal signal in response to the signals produced from the combinations of said multiplexed and square wave signals.
Claim 9
Dependent Claim
27 words
The modulator of claim 6 wherein said logical combining means comprises exclusive-OR gates which receive said multiplexed signals and said square wave signal as respective input signals.
Claim 10
Dependent Claim
15 words
The modulator of claim 6 wherein said generating means is a finite impulse response filter.
Claim 11
Dependent Claim
57 words
The modulator of claim 8 wherein said filter comprises a plurality of weighted taps for each data symbol, means for successively connecting each tap with the output of said combining means at least once during each cycle of said square wave signal, and means for summing the signal from each connected tap to generate said sinusoidal signal.
Claim 12
Dependent Claim
95 words
The modulator of claim 6 wherein each data element of the binary synchronous sequences comprises two bits of information and said multiplexer unit produces a multiplexed signal from one of the two bits of each sequence, further including a second multiplexing unit for producing second multiplexed signals from the other bit of each sequence, means for generating information signals having values related to the data contained in said second multiplexed signals, and means for selectively modifying said information signals in response to said signal produced from the combinations of said multiplexed and square wave signals.
Claim 13
Dependent Claim
30 words
The modulator of claim 10 wherein said values of information signals are voltage levels, and said selective modifying means includes for altering the polarity of said information signal voltage levels.
Claim 14
Dependent Claim
81 words
Apparatus for quadrature amplitude modulating two binary synchronous sequences, comprising: means for storing at least one bit of each of the two binary synchronous sequences; a multiplexer unit for switching between the stored bits of each of the two sequences at a frequency equal to twice a predetermined carrier frequency to produce a multiplexed signal; and means for logically combining the multiplexed signal with a square wave signal having a frequency equal to said carrier frequency of the quadrature amplitude modulation.
Claim 15
Dependent Claim
81 words
Apparatus for quadrature amplitude modulating two binary synchronous sequences, comprising: means for storing at least one bit of each of the two binary synchronous sequences; a multiplexer unit for switching between the stored bits of each of the two sequences at a frequency equal to twice a predetermined carrier frequency to produce a multiplexed signal; and means for logically combining the multiplexed signal with a square wave signal having a frequency equal to said carrier frequency of the quadrature amplitude modulation.
Claim 16
Dependent Claim
28 words
The modulator of claim 12 wherein said logical combining means comprises an exclusive-OR gate which receives said multiplexed signal and said square wave signal as respective input signals.
Claim 17
Dependent Claim
166 words
Apparatus for quadrature amplitude modulation of two binary synchronous sequences each having at least two bits of information per data symbol, comprising: means for separately storing the two bits of information in a data symbol of each of the two binary sequences; a first multiplexer unit operating at a frequency equal to twice a predetermined carrier frequency to produce a first multiplexed signal from one stored bit of each of the two binary sequences; means for logically combining the first multiplexed signal with a square wave signal having a frequency equal to said carrier frequency of the quadrature amplitude modulation; a second multiplexer unit operating at a frequency equal to twice said predetermined carrier frequency to produce a second multiplexed signal from the other stored bit of each of the two binary sequences; means for generating an amplitude modulated signal in response to said second multiplexed signal; and means for selectively modifying the polarity of said amplitude modulated signal in response to said first multiplexed signal.
Claim 18
Dependent Claim
166 words
Apparatus for quadrature amplitude modulation of two binary synchronous sequences each having at least two bits of information per data symbol, comprising: means for separately storing the two bits of information in a data symbol of each of the two binary sequences; a first multiplexer unit operating at a frequency equal to twice a predetermined carrier frequency to produce a first multiplexed signal from one stored bit of each of the two binary sequences; means for logically combining the first multiplexed signal with a square wave signal having a frequency equal to said carrier frequency of the quadrature amplitude modulation; a second multiplexer unit operating at a frequency equal to twice said predetermined carrier frequency to produce a second multiplexed signal from the other stored bit of each of the two binary sequences; means for generating an amplitude modulated signal in response to said second multiplexed signal; and means for selectively modifying the polarity of said amplitude modulated signal in response to said first multiplexed signal.
Claim 19
Independent Claim
119 words
A method for quadrature amplitude modulation of a carrier signal with two binary synchronous sequences, comprising the steps of: storing plural successive bits of each of the two binary synchronous sequences; for each pair of stored bits comprised of one bit from each of the two sequences, sequentially sampling the two bits in a pair at a frequency twice the frequency of the carrier signal to produce plural multiplexed signals; logically combining each of the multiplexed signals with a square wave signal having a frequency equal to that of the carrier frequency of the quadrature amplitude modulation to produce plural modulated signals; weighting each modulated signal in accordance with a desired transfer function; and summing the weighted modulated signals.
Claim 20
Independent Claim
119 words
A method for quadrature amplitude modulation of a carrier signal with two binary synchronous sequences, comprising the steps of: storing plural successive bits of each of the two binary synchronous sequences; for each pair of stored bits comprised of one bit from each of the two sequences, sequentially sampling the two bits in a pair at a frequency twice the frequency of the carrier signal to produce plural multiplexed signals; logically combining each of the multiplexed signals with a square wave signal having a frequency equal to that of the carrier frequency of the quadrature amplitude modulation to produce plural modulated signals; weighting each modulated signal in accordance with a desired transfer function; and summing the weighted modulated signals.
Claim 21
Dependent Claim
22 words
The method of claim 15 wherein said logical combining step comprises modulo-2 addition of the square wave signal and each multiplexed signal.
Claim 22
Dependent Claim
18 words
The method of claim 15 further including the step of converting the modulated signals into an analog signal.
Claim 23
Dependent Claim
107 words
Apparatus for quadrature amplitude modulating two binary synchronous sequences, comprising: means for storing plural successive bits of each of the two binary synchronous sequences; a multiplexer unit for switching between corresponding stored bits of each of the two sequences at a frequency equal to twice a predetermined carrier frequency to produce plural multiplexed signals; means for logically combining the multiplexed signals with a square wave signal having a frequency equal to said carrier frequency of the quadrature amplitude modulation to produce plural modulated signals; means for weighting each of the modulated signals in accordance with a desired transfer function; and means for summing the weighted modulated signals.
Claim 24
Dependent Claim
107 words
Apparatus for quadrature amplitude modulating two binary synchronous sequences, comprising: means for storing plural successive bits of each of the two binary synchronous sequences; a multiplexer unit for switching between corresponding stored bits of each of the two sequences at a frequency equal to twice a predetermined carrier frequency to produce plural multiplexed signals; means for logically combining the multiplexed signals with a square wave signal having a frequency equal to said carrier frequency of the quadrature amplitude modulation to produce plural modulated signals; means for weighting each of the modulated signals in accordance with a desired transfer function; and means for summing the weighted modulated signals.
Claim 25
Dependent Claim
31 words
The modulator of claim 18 wherein said logical combining means comprises exclusive-OR gates each of which receives one of said multiplexed signals and said square wave signal as respective input signals.
Claim 26
Dependent Claim
17 words
The modulator of claim 18 further including means for converting the modulated signals into an analog signal.
References Cited (Backward Citations)
US3349181A
Cited
US3793588A
Cited
US3985961A
Cited
US4347616A
Cited
US4455649A
Cited
US4527275A
Cited
US4550416A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-27 | 1990-10-27 | 1991-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-27 | 1994-10-27 | 1995-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-27 | 1998-10-27 | 1999-04-28 | $7700.00 | Window Closed / Lapsed |