US4667298A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for filtering high data rate signals
Assignee: United States Department of the Army
•
Filing: 1983-12-08
•
Granted: 1987-05-19
•
Expires: 2003-12-08
Abstract
Abstract Method and apparatus for filtering high data rate signals, using a digital type filter, without requiring an analog-to-digital converter or the multiplicaton of digital signals. The incoming signal is wideband filtered and then hard limited to produce a constant amplitude signal having either a first or second instantaneous value. The constant amplitude signal is periodically sampled and stored in a multi-bit digital shift register as logic 1 or 0 signals. In one embodiment, the logic 1 or 0 signals stored in the shift register bits are periodically read out, multiplied by respective weighting constants, and summed to provide a filtered analog output signal. In another embodiment, the combination of logic 1 and 0 signals stored in the shift register are periodically sampled and used to address a memory, which outputs a digital signal which is the calculated value of weighted sum for that shift register combination.
Inventors
- 👤 John O. Wedel, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:45
CPC Classifications
G; G06; G06J; G06J1/00; H; H03; H03H; H03H15/00; H03H17/00; H03H17/02; H03H17/06
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
218 words
Apparatus for filtering an analog signal, comprising: signal limiting means for hard limiting said analog signal to provide a constant amplitude signal having a first instantaneous value when the analog signal is above a predetermined level, and having a second instantaneous value when the analog signal is below said predetermined level, to thus remove amplitude fluctuations of said analog signal; clock means for generating timing signals; digital shift register means, actuated by said clock means and including a plurality of serially-arranged storage bits, for periodically sampling and storing said constant amplitude signal in a first bit as a logic 1 signal when the sampled constant amplitude signal has said first instantaneous value and as a logic 0 signal when the sampled constant amplitude signal has said second instantanteous value, the signal in each bit being shifted to a subsequent bit as a new signal is stored in the first bit and the signal stored in the last bit is lost, each bit having an output at which the signal stored in the bit can be sampled without changing the stored signal; and signal processing means for sampling each combination of logic 1 and 0 signals stored in said shift register menas, and generating an output signal corresponding to calculated values of weighted sum for said shift register combinations.
Claim 2
Dependent Claim
218 words
Apparatus for filtering an analog signal, comprising: signal limiting means for hard limiting said analog signal to provide a constant amplitude signal having a first instantaneous value when the analog signal is above a predetermined level, and having a second instantaneous value when the analog signal is below said predetermined level, to thus remove amplitude fluctuations of said analog signal; clock means for generating timing signals; digital shift register means, actuated by said clock means and including a plurality of serially-arranged storage bits, for periodically sampling and storing said constant amplitude signal in a first bit as a logic 1 signal when the sampled constant amplitude signal has said first instantaneous value and as a logic 0 signal when the sampled constant amplitude signal has said second instantanteous value, the signal in each bit being shifted to a subsequent bit as a new signal is stored in the first bit and the signal stored in the last bit is lost, each bit having an output at which the signal stored in the bit can be sampled without changing the stored signal; and signal processing means for sampling each combination of logic 1 and 0 signals stored in said shift register menas, and generating an output signal corresponding to calculated values of weighted sum for said shift register combinations.
Claim 3
Dependent Claim
61 words
Apparatus, as described in claim 1, in which said signal processing means comprise: signal summing means, having a plurality of inputs corresponding to the plurality of shift register bits, for generating an output signal which is the sum of signals supplied to said inputs; and a plurality of weighting resistors connected between the bit outputs and the summing means inputs, respectively.
Claim 4
Dependent Claim
88 words
Apparatus, as described in claim 1, in which said signal processing means comprises: memory means, having stored therein a plurality of numbers corresponding respectively to all possible combinations of logic 1 and 0 signals stored in said shift register means, each stored number being a calculated value of weighted sum for the corresponding shift register combination, said memory means being periodically activated by said clock means to sample each shift register combination and read out of said memory means the number corresponding to said sampled shift register combination.
Claim 5
Dependent Claim
26 words
Apparatus, as described in claim 3, which further comprises signal converting means for converting said number read out of said memory means to an analog signal.
Claim 6
Dependent Claim
167 words
Apparatus, as described in claim 1, in which said signal processing means comprise: a plurality of memory means, associated respectively with selected portions of the shift register bits, said bit portions together including all of the shift register bits, each memory means having stored therin a plurality of numbers corresponding respectively to all possible combinations of logic 1 and 0 signals stored in the associated portion of said shift register bits, each stored number being a calculated value of weighted sum for the corresponding combination stored in the associated bit portion, each memory means being periodically activated by said clock means to sample each combinations stored in the associated bit portion, each memory means being periodically activated by said clock means to sample each combination stored in the associated bit portion and read out of said memory means the number corresponding to said sampled combination; and summing means for summing the numbers read out of said plurality of memory means during each shift register combination sampling period.
Claim 7
Dependent Claim
26 words
Apparatus, as described in claim 5, which further comprises signal converting means for converting the summed numbers produced by said summing means to an analog signal.
Claim 8
Dependent Claim
34 words
Apparatus, as described in claim 1, in which said signal limiting means comprises: a filter circuit for wideband filtering said analog signal; and a limiter circuit for hard limiting the wideband filtered analog signal.
Claim 9
Dependent Claim
186 words
An analog signal filtering method, comprising the steps of: hard limiting said analog signal to provide a constant amplitude signal having a first instantaneous value when the analog signal is above a predetermined level, and having a second instantaneous value when the analog signal is below said predetermined level, to thus remove amplitude fluctuations of said analog signal; periodically sampling said constant amplitude signal; storing each sampled constant amplitude signal in a first bit of a multi-bit digital shift register as a logic 1 signal when the sampled constant amplitude signal has said first instantaneous value and as a logic 0 signal when the sampled constant amplitude signal has said second instantaneous value, the signal in each bit being shifted to a subsequent bit as a new signal is stored in the first bit and the signal in the last bit is lost; periodically sampling, without altering or destroying, the combination of logic 1 and 0 signals stored in said shift register bits; and converting said sampled shift register combinations into an output signal corresponding to calculated values of weighted sum for said shift register combinations.
Claim 10
Dependent Claim
186 words
An analog signal filtering method, comprising the steps of: hard limiting said analog signal to provide a constant amplitude signal having a first instantaneous value when the analog signal is above a predetermined level, and having a second instantaneous value when the analog signal is below said predetermined level, to thus remove amplitude fluctuations of said analog signal; periodically sampling said constant amplitude signal; storing each sampled constant amplitude signal in a first bit of a multi-bit digital shift register as a logic 1 signal when the sampled constant amplitude signal has said first instantaneous value and as a logic 0 signal when the sampled constant amplitude signal has said second instantaneous value, the signal in each bit being shifted to a subsequent bit as a new signal is stored in the first bit and the signal in the last bit is lost; periodically sampling, without altering or destroying, the combination of logic 1 and 0 signals stored in said shift register bits; and converting said sampled shift register combinations into an output signal corresponding to calculated values of weighted sum for said shift register combinations.
Claim 11
Dependent Claim
54 words
A method, as described in claim 8, wherein the step of converting said sampled shift register combinations further comprises the steps of: multiplying the sampled bit signals of each sampled shift register combination by respective weighting values; and summing the weighted bit signals of each sampled shift register combination to produce said output signal.
Claim 12
Dependent Claim
92 words
A method, as described in claim 8, wherein the step of converting said sampled shift register combinations further comprises the step of: using each sampled shift register combination as the address for a memory means having stored therein a plurality of numbers corresponding respectively to all possible shift register combinations, each stored number being a calculated value of weighted sum for the corresponding shift register combination, to thus read out of the memory means numbers corresponding to said sampled shift register combination in the form of digital signals constituting said output signal.
Claim 13
Dependent Claim
27 words
A method, as described in claim 10, which further comprises the step of converting the digital output signal of said memory means to an analog output signal.
Claim 14
Dependent Claim
162 words
A method, as described in claim 8, wherein the step of converting said sampled shift register combinations further comprises the steps of: using portins of each sampled shift register combination of logic 1 and 0 signals stored in the shift register bits as respective addresses for a plurality of memory means, each memory means having stored therein a plurality of numbers corresponding respectively to all possible combinatins of logic 1 and 0 signals stored in an associated portion of the shift register bits, each stored number being a calculated value of weighted sum for the corresponding combination of logic 1 and 0 signals stored in the associated portion of the shift register bits, to thus read out of said memory means numbers corresponding to respective portions of each sampled shift register combination in the form of digital signals; and summing the numbers read out of said plurality of memory means during each shift register combination sampling period, to produce said output signal.
Claim 15
Dependent Claim
25 words
A method, as described in claim 12, which further comprises the step of converting said output signal from a digital signal into an analog signal.
Claim 16
Dependent Claim
27 words
A method, as described in claim 8, which, before the step of hard limiting said analog signal, further comprises the step of wideband filtering said analog signal.
References Cited (Backward Citations)
US3521170A
Cited
US3573623A
Cited
US3605027A
Cited
US4001555A
Cited
US3949206A
Cited
US3963911A
Cited
US4156876A
Cited
US4121295A
Cited
US4120035A
Cited
US4323864A
Cited
US4313195A
Cited
US4322810A
Cited
US4374426A
Cited
US4435823A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-18 | 1990-11-17 | 1991-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-18 | 1994-11-17 | 1995-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-18 | 1998-11-17 | 1999-05-19 | $7700.00 | Window Closed / Lapsed |