US4323864A
Expired / Lapsed
US
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Binary transversal filter
Assignee: Fujitsu Ltd
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Filing: 1980-03-03
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Granted: 1982-04-06
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Expires: 2000-03-03
Abstract
Abstract A binary transversal filter which has a plurality of stages of shift registers that are driven by timing signals of a frequency which is a multiple of that of clock pulses being introduced, and a weighting circuit which weights outputs of shift registers of each of the stages, so that outputs of the weighting circuit can be synthesized. The characteristic feature of the present invention resides in the facts that NRZ signals are introduced into the shift registers, and the shift registers are driven by timing signals of a frequency which is a multiple of that of clock pulses of the NRZ signals.
Inventors
- 👤 Kazuo Ogawa
- 👤 Eiji Suzuki
- 👤 Osamu Kurita
- 👤 Izumi Horikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:39
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
143 words
A binary transversal filter for receiving NRZ input signals synchronously with clock pulses, comprising: a shift register, to which the NRZ input signals are fed directly, said register including a plurality of stages which are driven by timing signals of a frequency that is a multiplier M times that of the clock pulses of the input signals, a weighting circuit for weighting and synthesizing the outputs of each of the stages of said shift register, and a tap coefficient a n of said weighting circuit connected to each of the stages of said shift register being given by a sampling value of an interval T/M of an inverse Fourier transform a(t) of ##EQU9## wherein H(ω) denotes a transfer coefficient which gives a response that is to be found, T denotes a repetitive period of the input NRZ signals, and M represents said multiplier.
Claim 2
Dependent Claim
143 words
A binary transversal filter for receiving NRZ input signals synchronously with clock pulses, comprising: a shift register, to which the NRZ input signals are fed directly, said register including a plurality of stages which are driven by timing signals of a frequency that is a multiplier M times that of the clock pulses of the input signals, a weighting circuit for weighting and synthesizing the outputs of each of the stages of said shift register, and a tap coefficient a n of said weighting circuit connected to each of the stages of said shift register being given by a sampling value of an interval T/M of an inverse Fourier transform a(t) of ##EQU9## wherein H(ω) denotes a transfer coefficient which gives a response that is to be found, T denotes a repetitive period of the input NRZ signals, and M represents said multiplier.
Claim 3
Dependent Claim
97 words
A binary transversal filter as set forth in claim 1, wherein said shift register is driven by timing signals of a frequency two times that of the clock pulses of said NRZ signals, and said tap coefficient a n of said weighting circuit connected to each of the stages of said shift register is given by a sampling value of an interval T/2 of an inverse Fourier transform a(t) of ##EQU10## where H(ω) denotes a transfer coefficient which gives a response that is to be found, and T denotes a repetitive period of the input NRZ signals.
Claim 4
Dependent Claim
43 words
The filter of claim 1 or 2, wherein: each said tap coefficient a n of said weighting circuit is realized as a resistor having a value R n such that the product of R n and a n is constant for the filter.
Claim 5
Dependent Claim
17 words
The filter of claim 3, further comprising: an operational amplifier, operatively connected to all of said resistors.
Claim 6
Dependent Claim
19 words
The filter of claim 4, further comprising: a low-pass filter operatively connected to the output of said operational amplifier.
Claim 7
Dependent Claim
167 words
A binary transversal filter for receiving an NRZ input having a clock frequency 1/T and processing said input according to a transfer characteristic H(ω) comprising: a multiplier circuit for detecting the clock frequency of the NRZ input and generating timing signals at a frequency which is a preselected multiple M of the clock frequency; a shift register comprising (2n+1) sequentially connected stages, each stage being operatively connected to the timing signals generated by said multiplier circuit, and the first one of said stages being directly connected to the NRZ input; and a plurality of resistors, respectively connected at one terminal of each thereof to a corresponding stage of said shift register and connected at the other terminal of each thereof to a common output terminal to provide an output of said filter, wherein the value R k of the respective one of said resistors which is connected to the k-th stage of said shift register is given in relation to an arbitrary real constant C by: ##EQU11##
Claim 8
Dependent Claim
167 words
A binary transversal filter for receiving an NRZ input having a clock frequency 1/T and processing said input according to a transfer characteristic H(ω) comprising: a multiplier circuit for detecting the clock frequency of the NRZ input and generating timing signals at a frequency which is a preselected multiple M of the clock frequency; a shift register comprising (2n+1) sequentially connected stages, each stage being operatively connected to the timing signals generated by said multiplier circuit, and the first one of said stages being directly connected to the NRZ input; and a plurality of resistors, respectively connected at one terminal of each thereof to a corresponding stage of said shift register and connected at the other terminal of each thereof to a common output terminal to provide an output of said filter, wherein the value R k of the respective one of said resistors which is connected to the k-th stage of said shift register is given in relation to an arbitrary real constant C by: ##EQU11##
Claim 9
Dependent Claim
27 words
The filter of claim 6, further comprising: a low-pass filter, operatively connected between said common connection of said resistors and the output of said binary transversal filter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-05 | 1985-10-05 | 1986-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-05 | 1989-10-05 | 1990-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-05 | 1993-10-05 | 1994-04-06 | $7700.00 | Window Closed / Lapsed |