US3963911A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hybrid sample data filter
Assignee: United States Department of the Air Force
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Filing: 1975-04-22
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Granted: 1976-06-15
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Expires: 1995-04-22
Abstract
Abstract A sample data filter using a delta modulator to feed a shift register of which selected outputs are pulsewidth weighted. Each of the coefficient multipliers include a flip-flop fed by one of the taps of the shift register and triggered by a clock. A synchronous counter, common to each of the multipliers, is fed to a NAND gate that clears the flip-flop. Interposed between the counter and the NAND gate are a series of switches, one for each stage of the counter. The flip-flop controls a switch to a source of reference voltage and the output of this switch controlled voltage from each of the multipliers is summed and fed to a demodulator.
Inventors
- 👤 Lewis E. Franks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:31
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0614
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
239 words
A nonrecursive sample data filter comprising: a. a delta modulator; b. a shift register fed by the delta modulator having a series of selected output taps; c. a clock pulsing the delta modulator and the shift register; d. means for scaling the series of outputs of the shift register, the scaling means including 1. a reference voltage source, 2. a counter pulsed by the clock and having a series of complementary pairs of outputs, 3. a plurality of coefficient multipliers each fed by the plurality of complementary pairs of outputs of the counter and each including a. a plurality of coefficient setting switches each having an output terminal and a pair of selected input terminals, each of the pairs of input terminals connecting one of the complementary output pairs of the counter, b. a NAND gate fed by the output terminals of the plurality of coefficient setting switches, c. a flip-flop fed by one of the selected output taps of the shift register, triggered by the clock, and having a clearing terminal connected to the output of the NAND gate, d. a programmable switch having an input terminal connected to the reference voltage source and an output terminal, the programmable switch being activated by the output of the flip-flop; and e. a coefficient sign switch having an input terminal and a pair of selectable output terminals with the input terminal connected to the output terminal of the progammable switch,
Claim 2
Dependent Claim
239 words
A nonrecursive sample data filter comprising: a. a delta modulator; b. a shift register fed by the delta modulator having a series of selected output taps; c. a clock pulsing the delta modulator and the shift register; d. means for scaling the series of outputs of the shift register, the scaling means including 1. a reference voltage source, 2. a counter pulsed by the clock and having a series of complementary pairs of outputs, 3. a plurality of coefficient multipliers each fed by the plurality of complementary pairs of outputs of the counter and each including a. a plurality of coefficient setting switches each having an output terminal and a pair of selected input terminals, each of the pairs of input terminals connecting one of the complementary output pairs of the counter, b. a NAND gate fed by the output terminals of the plurality of coefficient setting switches, c. a flip-flop fed by one of the selected output taps of the shift register, triggered by the clock, and having a clearing terminal connected to the output of the NAND gate, d. a programmable switch having an input terminal connected to the reference voltage source and an output terminal, the programmable switch being activated by the output of the flip-flop; and e. a coefficient sign switch having an input terminal and a pair of selectable output terminals with the input terminal connected to the output terminal of the progammable switch,
Claim 3
Dependent Claim
31 words
means for summing the outputs of the coefficient multipliers, the summing means being connected to the coefficient sign switches; and e. a demodulator connector to the output of the summing means.
Claim 4
Dependent Claim
31 words
means for summing the outputs of the coefficient multipliers, the summing means being connected to the coefficient sign switches; and e. a demodulator connector to the output of the summing means.
Claim 5
Dependent Claim
240 words
A recursive sample data filter comprising: a. a delta modulator; b. a shift register fed by the delta modulator having a series of selected output taps; c. a clock pulsing the delta modulator and the shift register; d. means for scaling the series of outputs of the shift register, the scaling means including 1. a reference voltage source, 2. a counter pulsed by the clock and having a series of complementary pairs of outputs, 3. first and second pluralities of coefficient multipliers each fed by the plurality of complementary pairs of outputs of the counter, and each including a. a plurality of coefficient setting switches each having an output terminal and a pair of selected input terminals and each of the pairs of input terminals connecting one of the complementary output pairs of the counter, b. a NAND gate fed by the output terminals of the plurality of coefficient setting switches, c. a flip-flop fed by one of the selected taps of the shift register, triggered by the clock, and having a clearing terminal connected to the output of the NAND gate, d. a programmable switch having an input terminal connected to the reference voltage source and an output terminal, the programmable switch being activated by the output of the flip-flop; e. a coefficient sign switch having an input terminal and a pair of selectable output terminals with the input terminal connected to the output terminal of the programmable switch,
Claim 6
Dependent Claim
240 words
A recursive sample data filter comprising: a. a delta modulator; b. a shift register fed by the delta modulator having a series of selected output taps; c. a clock pulsing the delta modulator and the shift register; d. means for scaling the series of outputs of the shift register, the scaling means including 1. a reference voltage source, 2. a counter pulsed by the clock and having a series of complementary pairs of outputs, 3. first and second pluralities of coefficient multipliers each fed by the plurality of complementary pairs of outputs of the counter, and each including a. a plurality of coefficient setting switches each having an output terminal and a pair of selected input terminals and each of the pairs of input terminals connecting one of the complementary output pairs of the counter, b. a NAND gate fed by the output terminals of the plurality of coefficient setting switches, c. a flip-flop fed by one of the selected taps of the shift register, triggered by the clock, and having a clearing terminal connected to the output of the NAND gate, d. a programmable switch having an input terminal connected to the reference voltage source and an output terminal, the programmable switch being activated by the output of the flip-flop; e. a coefficient sign switch having an input terminal and a pair of selectable output terminals with the input terminal connected to the output terminal of the programmable switch,
Claim 7
Dependent Claim
43 words
first and second means for summing respectively the outputs of the first and second plurality of coefficient multipliers with the first summing means being fed back to the delta modulator; and e. a demodulator connected to the output of the second summing means.
Claim 8
Dependent Claim
43 words
first and second means for summing respectively the outputs of the first and second plurality of coefficient multipliers with the first summing means being fed back to the delta modulator; and e. a demodulator connected to the output of the second summing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-15 | 1979-12-15 | 1980-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-15 | 1983-12-15 | 1984-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-15 | 1987-12-15 | 1988-06-15 | $7700.00 | Window Closed / Lapsed |