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Patent US4743564A successfully refreshed from Google Patents.
US4743564A
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Method for manufacturing a complementary MOS type semiconductor device
Assignee: Toshiba Corp
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Filing: 1985-12-24
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Granted: 1988-05-10
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Expires: 2005-12-24
Abstract
Abstract A method for manufacturing a CMOS type semiconductor device is shown which includes the following steps. A first and a second conductive diffusion region are formed in a well region and a semiconductor substrate, respectively, and a gate electrode is formed thereon. An insulation layer is formed on the semiconductor substrate and the well region. A contact hole is opened by selectively removing the insulation layer corresponding to the first and the second conductive diffusion regions. At least one metal layer selected from a group consisting of metal and metal silicide having a high melting point is formed on an exposed surface of the first and the second conductive diffusion regions. The semiconductor substrate is heated to melt at least part of the insulation layer and form a tapered portion. A wiring layer is formed on the contact hole. This method prevents the contact resistance from increasing, the impurity of one region from diffusing into the other impurity regions, the impurity of the impurity regions from decreasing, and improves the reliability of the wiring layer by forming a tapered contact hole. These advantages permit high component density by miniaturizing the device.
Inventors
- 👤 Masaki Sato
- 👤 Kazuyoshi Shinada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:59
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0186; H10D84/02; H10D84/03; H10D84/038; H10P; H10P95/00; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
217 words
A method for manufacturing a complementary MOS semiconductor device on a semiconductor substrate having a well region formed in a portion of the surface of said substrate, the mthod comprising the sequential steps of: forming a structure having a first conductive diffusion region containing a first conductive impurity in the surface of said semiconductor substrate, a second conductive duffusion region containing a second conductive impurity in said well region of said semiconductor substrate, and a gate electrode on each of said conductive diffusion regions; forming a silicate glass insulation layer containing one of said first and second conductive impurities overlying said semiconductor substrate, said well region, said conductive diffusion regions, and said gate electrodes; opening a contact hole by selectively removing a portion of said insulation layer overlying said first conductive diffusion region and a portion of said insulation layer overlying said second conductive diffusion region; forming at least one metal layer on the surfaces of said first and second conductive duffusion region exposed by said contact holes, said metal being selected from the group consisting of metal and metal silicide; heating said semiconductor substrate to melt at least part of said insulation layer and form a tapered portion thereof adjacent said contact hole; and forming a wiring layer on said metal layer in said contact hole.
Claim 2
Independent Claim
217 words
A method for manufacturing a complementary MOS semiconductor device on a semiconductor substrate having a well region formed in a portion of the surface of said substrate, the mthod comprising the sequential steps of: forming a structure having a first conductive diffusion region containing a first conductive impurity in the surface of said semiconductor substrate, a second conductive duffusion region containing a second conductive impurity in said well region of said semiconductor substrate, and a gate electrode on each of said conductive diffusion regions; forming a silicate glass insulation layer containing one of said first and second conductive impurities overlying said semiconductor substrate, said well region, said conductive diffusion regions, and said gate electrodes; opening a contact hole by selectively removing a portion of said insulation layer overlying said first conductive diffusion region and a portion of said insulation layer overlying said second conductive diffusion region; forming at least one metal layer on the surfaces of said first and second conductive duffusion region exposed by said contact holes, said metal being selected from the group consisting of metal and metal silicide; heating said semiconductor substrate to melt at least part of said insulation layer and form a tapered portion thereof adjacent said contact hole; and forming a wiring layer on said metal layer in said contact hole.
Claim 3
Dependent Claim
39 words
The method according to claim 1, further including a step of ion-implanting a first conductive impurity into said first conductive diffusion region and a second conductive impurity into said second conductive diffusion region after said metal layer is formed.
Claim 4
Dependent Claim
31 words
A method according to claim 1, further including the step of ion-implanting silicon ions into said first conductive diffusion region and second conductive diffusion region after said metal layer is formed.
Claim 5
Dependent Claim
17 words
A method according to claim 1, wherein said metal layer consists of a tungsten silicide and tungsten.
Claim 6
Dependent Claim
15 words
A method according to claim 1, wherein said heating step is performed using light radiation.
Claim 7
Dependent Claim
15 words
A method according to claim 5, wherein said light radiation is performed by lamp annealing.
Claim 8
Independent Claim
138 words
A method for manufacturing a complementary MOS semiconductor device, comprising the sequential steps of: forming a structure having a first conductive diffusion region in a well region of a semiconductor substrate, a second conductive diffusion region in said semiconductor substrate and a gate electrode thereon; forming at least one metal layer selected from a group consisting of metal and metal silicide on an exposed surface of said first conductive diffusion region and said second conductive diffusion region opening a contact hole by selectively removing that portion of said insulation layer corresponding to said first conductive diffusion region and said second conductive diffusion region; heating said semiconductor substrate to melt at least part of said insulation layer and form a tapered portion thereof in the region of said contact hole; and forming a wiring layer on said contact hole.
Claim 9
Independent Claim
138 words
A method for manufacturing a complementary MOS semiconductor device, comprising the sequential steps of: forming a structure having a first conductive diffusion region in a well region of a semiconductor substrate, a second conductive diffusion region in said semiconductor substrate and a gate electrode thereon; forming at least one metal layer selected from a group consisting of metal and metal silicide on an exposed surface of said first conductive diffusion region and said second conductive diffusion region opening a contact hole by selectively removing that portion of said insulation layer corresponding to said first conductive diffusion region and said second conductive diffusion region; heating said semiconductor substrate to melt at least part of said insulation layer and form a tapered portion thereof in the region of said contact hole; and forming a wiring layer on said contact hole.
Claim 10
Dependent Claim
39 words
A method according to claim 7, further including the step of ion-implanting a first conductive impurity into said first conductive diffusion region and a second conductive impurity into said second conductive diffusion region after said metal layer is formed.
Claim 11
Dependent Claim
32 words
A method according to claim 7, further including the step of ion-implanting silicon ions into said first conductive diffusion region and said second conductive diffusion region after said metal layer is formed.
Claim 12
Dependent Claim
17 words
A method according to claim 7, wherein said metal layer consists of a tungsten silicide and tungsten.
Claim 13
Dependent Claim
15 words
A method according to claim 7, wherein said heating step is performed using light radiation.
Claim 14
Dependent Claim
16 words
A method according to claim 11, wherein said light radiation method is performed by lamp annealing.
References Cited (Backward Citations)
US3986903A
Cited
US4348802A
Cited
SU880174A1
Cited
US4404733A
Cited
US4349584A
Cited
US4551908A
Cited
US4363830A
Cited
US4378628A
Cited
US4442591A
Cited
US4528744A
Cited
JPS59119746A
Cited
JPS59201426A
Cited
JPS60132345A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |