US4740997A
Expired / Lapsed
US
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Band clock offset phase locked loop
Assignee: Telogy Networks Inc
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Filing: 1986-10-08
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Granted: 1988-04-26
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Expires: 2006-10-08
Abstract
Abstract A quadrature differential phase shift keyed signal demodulator for use in a modem is shown. A delay circuit (12) delays an input signal for a portion of a baud time. Synchronous detectors (21, 23) mix the original and delayed input signals with coherent reference signals to obtain detected outputs which are alternately provided to a processor (60) by a multiplexer (25). The processor (60) determines the phase shift and provides the demodulated data. An offset baud clock phase locked loop (40) provides a baud clock which is offset by a ninety degree phase lag. The offset baud clock causes the multiplexer (25) to provide detected outputs to the processor (60) for the center one-half of each baud. The result is a demodulator with fewer components and an improved data error rate.
Inventors
- 👤 Dale A. Heatherington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:15
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2275
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
154 words
A baud clock offset phase locked loop for providing an offset baud clock signal having the same frequency as a characteristic baud rate of an input signal and being displaced from the beginning of a baud time by a predetermined phase angle, comprising in combination: means for generating a clock signal; delay means responsive to said input signal for providing a delayed input signal which lags said input signal by a predetermined portion of a baud time; phase change detector means responsive to said offset baud clock signal, to said input signal, and to said delayed input signal for providing a phase error output a latch responsive to a sample clock and to said phase change detector means for storing said phase error output signal; and counter means responsive to the output of said latch and to the frequency of said clock signal for providing said offset baud clock signal and said sample clock.
Claim 2
Dependent Claim
154 words
A baud clock offset phase locked loop for providing an offset baud clock signal having the same frequency as a characteristic baud rate of an input signal and being displaced from the beginning of a baud time by a predetermined phase angle, comprising in combination: means for generating a clock signal; delay means responsive to said input signal for providing a delayed input signal which lags said input signal by a predetermined portion of a baud time; phase change detector means responsive to said offset baud clock signal, to said input signal, and to said delayed input signal for providing a phase error output a latch responsive to a sample clock and to said phase change detector means for storing said phase error output signal; and counter means responsive to the output of said latch and to the frequency of said clock signal for providing said offset baud clock signal and said sample clock.
Claim 3
Dependent Claim
40 words
The apparatus as in claim 1, wherein said clock signal is a first clock signal and further comprising; means for generating a second clock signal; and wherein said delay means comprises a shift register responsive to said second clock signal.
Claim 4
Dependent Claim
21 words
The apparatus as in claim 1 in which said predetermined portion of a baud time is one-half of a baud time.
Claim 5
Dependent Claim
61 words
The apparatus as in claim 1 in which said phase change detector means comprises two EXCLUSIVE-OR gates, a first said gate being responsive to said input signal and said delayed input signal for providing a gated signal, and a second said gate being responsive to said gated signal and said offset baud clock signal for providing said phase error output signal.
Claim 6
Dependent Claim
17 words
The apparatus as in claim 1 in which said predetermined phase angle is minus ninety degrees (-90°).
Claim 7
Dependent Claim
52 words
The apparatus as in claim 1 in which said counter means comprises a digital counter/divider and a microprocessor, said counter/divider being responsive to said output of said latch and to said clock signal for providing said sample clock, said microprocessor being responsive to said sample clock for providing said offset baud clock.
Claim 8
Dependent Claim
170 words
A baud clock offset phase locked loop for providing an offset baud clock signal having the same frequency as a characteristic baud rate of an input signal and being displaced from the beginning of a baud time by a predetermined phase angle, comprising in combination: means for generating a clock signal; delay means responsive to said input signal for providing a delayed input signal which lags said input signal by a predetermined portion of a baud time; first gating means responsive to said input signal and said delayed input signal for providing a gated signal; second gating means responsive to said offset baud clock signal and said gated signal for providing a phase error output signal; latching means responsive to a sample clock and to said second gating means for storing said phase error output signal; means responsive to the output of said latching means and to said clock signal for providing said sample clock; and divider means responsive to said sample clock for providing said offset baud clock signal.
Claim 9
Dependent Claim
170 words
A baud clock offset phase locked loop for providing an offset baud clock signal having the same frequency as a characteristic baud rate of an input signal and being displaced from the beginning of a baud time by a predetermined phase angle, comprising in combination: means for generating a clock signal; delay means responsive to said input signal for providing a delayed input signal which lags said input signal by a predetermined portion of a baud time; first gating means responsive to said input signal and said delayed input signal for providing a gated signal; second gating means responsive to said offset baud clock signal and said gated signal for providing a phase error output signal; latching means responsive to a sample clock and to said second gating means for storing said phase error output signal; means responsive to the output of said latching means and to said clock signal for providing said sample clock; and divider means responsive to said sample clock for providing said offset baud clock signal.
Claim 10
Dependent Claim
12 words
The apparatus of claim 7 wherein said divider means comprises a microprocessor.
Claim 11
Dependent Claim
19 words
The apparatus of claim 7 wherein said means responsive to the output of said latching means comprises a counter/divider.
Claim 12
Dependent Claim
13 words
The apparatus of claim 7 wherein said delay means comprises a shift register.
Claim 13
Dependent Claim
21 words
The appratus as in claim 7 in which said predetermined portion of a baud time is one-half of a baud time.
Claim 14
Dependent Claim
17 words
The apparatus as in claim 7 in which said predetermined phase angle is minus ninety degrees (-90°).
Claim 15
Dependent Claim
14 words
The apparatus of claim 7 wherein said first gating means comprises an exclusive-OR gate.
Claim 16
Dependent Claim
14 words
The apparatus of claim 7 wherein said second gating means comprises an exclusive-OR gate.
Claim 17
Dependent Claim
14 words
The apparatus of claim 13 wherein said second gating means comprises an exclusive-OR gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-26 | 1991-10-26 | 1992-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-26 | 1995-10-26 | 1996-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-26 | 1999-10-26 | 2000-04-26 | $7700.00 | Window Closed / Lapsed |