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US4740914A
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Address generator
Assignee: AG Communication Systems Corp
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Filing: 1984-12-31
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Granted: 1988-04-26
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Expires: 2004-12-31
Abstract
Abstract An address generator which provides addresses for machine storage and software retrieval of computer status information. A counter is used to generate address signals in a descending order until it is disabled by a computer during alarm conditions. Under such conditions the counter provides a bias address for referencing the most recent status word. A gating circuit gates computer generated address signals to an adder circuit during the alarm conditions. The adder circuit adds the computer generated address signals to the counter generated bias signal to provide address signals which reference physical storage locations in a memory.
Inventors
- 👤 Robert J. Abrant
- 👤 Michael D. Martys
- 👤 George K. Tarleton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:10
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0766; G06F11/0772; G06F11/0706; G06F11/073; G06F11/14; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/20
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
219 words
An address generator for use in a computer system that includes a clock circuit operated to provide periodic clock signals, and a computer operated to provide a disable signal, an enable signal, a stop count signal, a start count signal and a plurality of address signals, said address generator comprising: counting means connected to said computer and said clock circuit and operated in response to said enable signal to count said clock pulses and to provide counter signals representative of the number of clock pulses counted, said counter signals having predetermined minimum and maximum values, said counting means being further operated in response to detection of said disable signal to inhibit the counting of said clock pulses and to provide signals representative of the number of clock pulses counted immediately before detection of said disable signal; an adder circuit connected to said counting means; and gating means connected between said computer and said adder circuit and operated in response to said start count signal to provide a plurality of address signals of predetermined value, and further operated in response to said stop count signal to gate said address signals from said computer to said adder circuit; said adder circuit being operated to add said counter signals to said address signals of predetermined value or to said gated address signals.
Claim 2
Dependent Claim
219 words
An address generator for use in a computer system that includes a clock circuit operated to provide periodic clock signals, and a computer operated to provide a disable signal, an enable signal, a stop count signal, a start count signal and a plurality of address signals, said address generator comprising: counting means connected to said computer and said clock circuit and operated in response to said enable signal to count said clock pulses and to provide counter signals representative of the number of clock pulses counted, said counter signals having predetermined minimum and maximum values, said counting means being further operated in response to detection of said disable signal to inhibit the counting of said clock pulses and to provide signals representative of the number of clock pulses counted immediately before detection of said disable signal; an adder circuit connected to said counting means; and gating means connected between said computer and said adder circuit and operated in response to said start count signal to provide a plurality of address signals of predetermined value, and further operated in response to said stop count signal to gate said address signals from said computer to said adder circuit; said adder circuit being operated to add said counter signals to said address signals of predetermined value or to said gated address signals.
Claim 3
Dependent Claim
49 words
An address generator as claimed in claim 1, wherein said gating means comprises a plurality of AND gates, each operated in response to said start count and stop count signals to provide said address signals of predetermined value and to gate an associated on of said address signals, respectively.
Claim 4
Dependent Claim
16 words
An address generator as claimed in claim 2, wherein said gating means comprises four AND gates.
Claim 5
Dependent Claim
17 words
An address generator as claimed in claim 1, wherein said counting means comprises a four bit counter.
Claim 6
Dependent Claim
17 words
An address generator as claimed in claim 1, wherein said adder circuit comprises a four bit adder.
Claim 7
Dependent Claim
25 words
An address generator as claimed in claim 1, wherein said counter is a down counter and said computer sequentially provides address signals of increasing value.
Claim 8
Dependent Claim
25 words
An address generator as claimed in claim 1, wherein said counter is an up counter and said computer sequentially provides address signals of decreasing value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-26 | 1991-10-26 | 1992-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-26 | 1995-10-26 | 1996-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-26 | 1999-10-26 | 2000-04-26 | $7700.00 | Window Closed / Lapsed |