Patent US4737835A successfully refreshed from Google Patents.
US4737835A
Expired / Lapsed
US
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Read only memory semiconductor device
Assignee: Toshiba Corp
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Filing: 1986-10-16
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Granted: 1988-04-12
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Expires: 2006-10-16
Abstract
Abstract A read only memory contains a conductive layer of polysilicon which contacts the drains of memory cell MOS transistors and lies near and on a gate electrode. A data line made of aluminum and the drain of the MOS transistors are interconnected through the conductive layer. A method of manufacturing the ROM such structure is also disclosed.
Inventors
- 👤 Shoji Ariizumi
- 👤 Taira Iwase
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:11
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/34; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
169 words
A read only memory semiconductor device comprising: a pair of regions of a first conductivity type formed in a semiconductor substrate of a second conductivity type opposite to said first conductivity type, the pair of regions individually forming drain and source regions of an MOS transistor; a first gate insulation film formed on said substrate; a first gate electrode conductive layer formed on said gate insulation film; a second insulation film formed on said gate electrode conductive layer; a second conductive layer of said first conductivity type formed on one region of said pair of regions, the second conductive layer extending through said second insulation film; a third insulation film formed on said second conductive layer and having a contact hole, the contact hole being partially above said one region; and a third conductive layer formed on said third insulation film, the third conductive layer extending into said contact hole and contacting said second conductive layer, a continuous portion of the third conductive layer being above said one region.
Claim 2
Dependent Claim
169 words
A read only memory semiconductor device comprising: a pair of regions of a first conductivity type formed in a semiconductor substrate of a second conductivity type opposite to said first conductivity type, the pair of regions individually forming drain and source regions of an MOS transistor; a first gate insulation film formed on said substrate; a first gate electrode conductive layer formed on said gate insulation film; a second insulation film formed on said gate electrode conductive layer; a second conductive layer of said first conductivity type formed on one region of said pair of regions, the second conductive layer extending through said second insulation film; a third insulation film formed on said second conductive layer and having a contact hole, the contact hole being partially above said one region; and a third conductive layer formed on said third insulation film, the third conductive layer extending into said contact hole and contacting said second conductive layer, a continuous portion of the third conductive layer being above said one region.
Claim 3
Dependent Claim
16 words
A semiconductor device according to claim 1, wherein said second conductive layer is formed of polysilicon.
Claim 4
Dependent Claim
27 words
A semiconductor device according to claim 1, wherein said one of the pair of semiconductor regions has a thicker part thereof which contacts said second conductive layer.
References Cited (Backward Citations)
US4558343A
Cited
US4324238A
Cited
US4291322A
Cited
US4403394A
Cited
US4649412A
Cited
US4624959A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-12 | 1991-10-12 | 1992-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-12 | 1995-10-12 | 1996-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-12 | 1999-10-12 | 2000-04-12 | $7700.00 | Window Closed / Lapsed |