Patent US4737831A successfully refreshed from Google Patents.
US4737831A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with self-aligned gate structure and manufacturing process thereof
Assignee: Toshiba Corp
•
Filing: 1986-09-11
•
Granted: 1988-04-12
•
Expires: 2006-09-11
Abstract
Abstract A semiconductor device having a new structure of source and drain regions. A semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, an impurity region of a second conductivity type formed on the semiconductor substrate, and a metal pattern formed on the impurity region and isolated by a plurality of grooves. A gate insulation film is formed on the bottom and the inner wall of at least one of the grooves, and a conductor to be a gate electrode is formed on the gate insulation film to be buried in this groove.
Inventors
- 👤 Hiroshi Iwai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:11
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D10/00; H10D10/80; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/027; H10D30/0273; H10D30/60; H10D30/637; H10D62/80; H10D62/83; H10D62/834; H10D64/00; H10D64/01; H10D64/025; H10D64/027; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/60; H10D64/62
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
186 words
A semiconductor device with a self-aligned gate structure and a self-aligned field region, comprising: (a) a semiconductor substrate of a first conductivity type; (b) an impurity layer of a second conductivity type formed on said semiconductor substrate and separated by a first groove into a first impurity portion and a second impurity portion; (c) a metal pattern formed on said impurity layer and separated by said first groove into a first metal portion and a second metal portion, the first impurity portion and the first metal portion on the first impurity portion constituting a source region of a transistor, and the second impurity portion and the second metal portion constituting a drain region of the transistor, and one end of at least one of the source region and the drain region being defined by a second groove; (d) a gate insulation film formed on at least a side wall of said first groove; (e) a gate electrode formed of a conductor buried in said first groove; and (f) a field region formed of a insulator formed at least on the inner surface of said second groove.
Claim 2
Dependent Claim
186 words
A semiconductor device with a self-aligned gate structure and a self-aligned field region, comprising: (a) a semiconductor substrate of a first conductivity type; (b) an impurity layer of a second conductivity type formed on said semiconductor substrate and separated by a first groove into a first impurity portion and a second impurity portion; (c) a metal pattern formed on said impurity layer and separated by said first groove into a first metal portion and a second metal portion, the first impurity portion and the first metal portion on the first impurity portion constituting a source region of a transistor, and the second impurity portion and the second metal portion constituting a drain region of the transistor, and one end of at least one of the source region and the drain region being defined by a second groove; (d) a gate insulation film formed on at least a side wall of said first groove; (e) a gate electrode formed of a conductor buried in said first groove; and (f) a field region formed of a insulator formed at least on the inner surface of said second groove.
Claim 3
Dependent Claim
36 words
The semiconductor device according to claim 1, wherein the impurity concentration of said impurity layer adjacent to portions through which said first groove is formed is lower than that of other portions of said impurity layer.
Claim 4
Dependent Claim
39 words
The semiconductor device according to claim 1, wherein a side wall portion of said gate insulation film at a side of said metal pattern is thicker than a bottom portion thereof at a side of said semiconductor substrate thereof.
References Cited (Backward Citations)
US3648125A
Cited
US4108686A
Cited
US4206005A
Cited
US4462040A
Cited
US4513303A
Cited
US4324038A
Cited
JPS5861645A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-12 | 1991-10-12 | 1992-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-12 | 1995-10-12 | 1996-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-12 | 1999-10-12 | 2000-04-12 | $7700.00 | Window Closed / Lapsed |