US4513303A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned metal field effect transistor integrated circuit
Assignee: International Business Machines Corp
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Filing: 1982-08-06
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Granted: 1985-04-23
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Expires: 2002-08-06
Abstract
Abstract A self-aligned metal field effect transistor is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar.
Inventors
- 👤 Shakir A. Abbas
- 👤 Ingrid E. Magdo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:18
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D30/027; H10D30/0273; H10D64/00; H10D64/01; H10D64/011; H10D64/018; H10D64/025; H10D64/027; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10P; H10P76/00; H10P76/40; H10P76/408; H10D30/0217; H10D64/017
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
113 words
A field effect transistor self-aligned dynamic RAM integrated circuit structure comprising: a silicon body having said field effect transistor dynamic RAM devices therein with regions of said devices extending to the major surface of said body; silicon dioxide regions within said body for isolating groupings of said devices from one another; at least some of said groupings of said devices including a PN junction drain and capacitor structure; a pattern of narrow dimensioned dielectric regions on said surface of said body; and electrical contacts to said drain and capacitor filling the spaces between said narrow dimensioned regions and which contacts are self-aligned to said narrow regions and substantially planar with said narrow regions.
Claim 2
Dependent Claim
113 words
A field effect transistor self-aligned dynamic RAM integrated circuit structure comprising: a silicon body having said field effect transistor dynamic RAM devices therein with regions of said devices extending to the major surface of said body; silicon dioxide regions within said body for isolating groupings of said devices from one another; at least some of said groupings of said devices including a PN junction drain and capacitor structure; a pattern of narrow dimensioned dielectric regions on said surface of said body; and electrical contacts to said drain and capacitor filling the spaces between said narrow dimensioned regions and which contacts are self-aligned to said narrow regions and substantially planar with said narrow regions.
Claim 3
Dependent Claim
30 words
The field effect transistor integrated circuit structure of claim 1 wherein said electrical contacts are composed of a first layer of doped polycrystalline silicon and a second layer of metal.
Claim 4
Dependent Claim
164 words
A substantially planar self-aligned field effect transistor integrated circuit structure comprising: a silicon body; a pattern of narrow dimensioned dielectric regions on a major surface of said body; a gate dielectric layer on the said surface of said body forming a portion of said field effect transistor structure between certain of said narrow dimensioned regions; PN junction regions within said body forming a portion of said field effect transistor structure and in close proximity to and associate with the channel under said gate dielectric layer; a layer of doped polycrystalline silicon which is substantially shorter than the height of said certain narrow dimensioned regions on said gate dielectric; and metal electrical contacts to said PN junction regions by filling spaces between said pattern of narrow dimensioned region and to said layer of polycrystalline silicon by filling the spaces between said certain of said narrow dimensioned regions which contacts are self-aligned to said narrow regions and substantially planar with the tops of said narrow regions.
Claim 5
Dependent Claim
164 words
A substantially planar self-aligned field effect transistor integrated circuit structure comprising: a silicon body; a pattern of narrow dimensioned dielectric regions on a major surface of said body; a gate dielectric layer on the said surface of said body forming a portion of said field effect transistor structure between certain of said narrow dimensioned regions; PN junction regions within said body forming a portion of said field effect transistor structure and in close proximity to and associate with the channel under said gate dielectric layer; a layer of doped polycrystalline silicon which is substantially shorter than the height of said certain narrow dimensioned regions on said gate dielectric; and metal electrical contacts to said PN junction regions by filling spaces between said pattern of narrow dimensioned region and to said layer of polycrystalline silicon by filling the spaces between said certain of said narrow dimensioned regions which contacts are self-aligned to said narrow regions and substantially planar with the tops of said narrow regions.
Claim 6
Dependent Claim
23 words
The integrated circuit structure of claim 3 wherein silicon dioxide regions with said body dielectrically isolates certain of said transistors from similar transistors.
Claim 7
Dependent Claim
16 words
The integrated circuit structure of claim 3 wherein said PN junction regions are sources and drains.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1988-04-22 | 1988-10-22 | 1989-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-22 | 1992-10-22 | 1993-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-22 | 1996-10-22 | 1997-04-23 | $7700.00 | Window Closed / Lapsed |