Patent US4063945A successfully refreshed from Google Patents.
Patent US2825880A successfully refreshed from Google Patents.
Patent US1845754A successfully refreshed from Google Patents.
Patent US4478094A successfully refreshed from Google Patents.
Patent US4733403A successfully refreshed from Google Patents.
US4733403A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital zero IF selectivity section
Assignee: Motorola Solutions Inc
•
Filing: 1986-05-12
•
Granted: 1988-03-22
•
Expires: 2006-05-12
Abstract
Abstract Disclosed is a digital zero-IF selectivity section circuit which operates on a recovered input signal, digitally clocked by a first clock at a rate of FS, in receiver device. The circuit uses a second clock operating at a lesser rate than the first clock to clock an N-order FIR digital filtering means to selectively band-limit the frequency spectrum of the recovered input signal. A second digital filtering means is coupled to the output of the first FIR digital filtering means. The second digital filtering means operates at a clock speed less than or equal to the second clock speed. The second digital filtering means is used to further selectively band-limit the frequency spectrum of the recovered input signal.
Inventors
- 👤 Daniel A. Simone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:58
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/06; H04B1/10; H03; H03D; H03D3/00; H03D3/007; H03D2200/00; H03D2200/0041; H03D2200/0054; H03D2200/0056; H03D2200/006; H03D2200/009; H03D2200/0092; H03D3/006; H03D7/00; H03D7/16; H03D7/165
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
117 words
A digital zero-IF selectivity section circuit operating on a recovered input signal, digitally clocked by a first clock at a rate of FS, in a receiver device, comprising: second clock means for providing a periodic clock signal at a lesser rate than said first clock means; first N-order decimating FIR digital filtering means, coupled to said second clock means, for selectively band-limiting the frequency spectrum of the recovered input signal; one or more second digital filtering means, coupled to the output of said first N-order decimating FIR digital filtering means and operating at a clock rate less than or equal to said second clock rate, for further selectively band-limiting the frequency spectrum of the recovered input signal.
Claim 2
Dependent Claim
117 words
A digital zero-IF selectivity section circuit operating on a recovered input signal, digitally clocked by a first clock at a rate of FS, in a receiver device, comprising: second clock means for providing a periodic clock signal at a lesser rate than said first clock means; first N-order decimating FIR digital filtering means, coupled to said second clock means, for selectively band-limiting the frequency spectrum of the recovered input signal; one or more second digital filtering means, coupled to the output of said first N-order decimating FIR digital filtering means and operating at a clock rate less than or equal to said second clock rate, for further selectively band-limiting the frequency spectrum of the recovered input signal.
Claim 3
Dependent Claim
25 words
The digital zero-IF selectivity section circuit, according to claim 1, wherein said lesser rate of said second clock means is one-half the first clock rate.
Claim 4
Dependent Claim
25 words
The digital zero-IF selectivity section circuit, according to claim 1, further including means for coupling said second clock means to said second digital filter means.
Claim 5
Dependent Claim
36 words
The digital zero-IF selectivity section circuit, according to claim 1, including a third clock means operating the second digital filter means at a clock rate defined according to the order of said second digital filter means.
Claim 6
Dependent Claim
34 words
The digital zero-IF selectivity section circuit, according to claim 1, further including means for sampling the recovered input signal at a further reduced rate after it is filtered by said second digital filter means.
Claim 7
Dependent Claim
31 words
The digital zero-IF selectivity section circuit, according to claim 1, wherein said first N-order decimating FIR digital filter means includes means for sampling the recovered input signal at a reduced rate.
Claim 8
Dependent Claim
32 words
The digital zero-IF selectivity section circuit, according to claim 6, further including means for coupling said second clock means to said means for sampling the recovered input signal at a reduced rate.
Claim 9
Dependent Claim
35 words
The digital zero-IF selectivity section circuit, according to claim 1, further including a plurality of latches, clocked by said first clock means, for sequentially latching data to said first N-order decimating FIR digital filter means.
Claim 10
Dependent Claim
24 words
The digital zero-IF selectivity section circuit, according to claim 1, wherein said first N-order decimating FIR digital filter means includes an N-order FIR filter.
Claim 11
Dependent Claim
37 words
The digital zero-IF selectivity section circuit, according to claim 9, wherein said N-order decimating FIR filter means includes a plurality of. latches, clocked by said second clock means, for sequentially latching data from the recovered input signal.
Claim 12
Dependent Claim
41 words
The digital zero-IF selectivity section circuit, according to claim 10, wherein said N-order decimating FIR filter includes at least one additional latch, clocked by said second clock means, for sequentially latching data from selected one of said second plurality of latches.
Claim 13
Dependent Claim
33 words
The digital zero-IF selectivity section circuit, according to claim 9, wherein said N-order decimating FIR filter includes means for multiplying coefficients corresponding to a predetermined filtering algorithm of said N-order decimating FIR filter.
Claim 14
Dependent Claim
29 words
The digital zero-IF selectivity section circuit, according to claim 9, wherein said N-order decimating FIR filter includes means for adding decimated samples to generate a band-limited recovered input signal.
Claim 15
Dependent Claim
16 words
The digital zero-IF selectivity section circuity according to claim 1, including means to prevent aliasing error.
Claim 16
Dependent Claim
125 words
In a digital zero-IF selectivity section circuit operating on a recovered input signal, clocked by a first clock at a rate of FS, in a receiver device, a method of filtering, comprising the steps of: providing a second periodic clock signal at a lesser rate than said first clock; digitally filtering, by a first N-order decimating FIR filter means coupled to said second clock, to selectively band-limit the frequency spectrum of the recovered input signal; digitally filtering, by one or more second digital filtering means coupled to the output of said first N-order decimating FIR digital filtering means and operating at a clock rate less than or equal to said second clock signal, to further selectively band-limit the frequency spectrum of the recovered input signal.
Claim 17
Dependent Claim
125 words
In a digital zero-IF selectivity section circuit operating on a recovered input signal, clocked by a first clock at a rate of FS, in a receiver device, a method of filtering, comprising the steps of: providing a second periodic clock signal at a lesser rate than said first clock; digitally filtering, by a first N-order decimating FIR filter means coupled to said second clock, to selectively band-limit the frequency spectrum of the recovered input signal; digitally filtering, by one or more second digital filtering means coupled to the output of said first N-order decimating FIR digital filtering means and operating at a clock rate less than or equal to said second clock signal, to further selectively band-limit the frequency spectrum of the recovered input signal.
Claim 18
Dependent Claim
22 words
The method of filtering, according to claim 15, wherein said lesser rate of said second clock is one-half the first clock rate.
Claim 19
Dependent Claim
26 words
The method of filtering, according to claim 15, further including the step of providing means for coupling said second clock to said second digital filter means.
Claim 20
Dependent Claim
38 words
The method of filtering, according to claim 15, including the step of providing a third clock means operating the second digital filter means at a clock rate defined according to the order of said second digital filter means.
Claim 21
Dependent Claim
35 words
The method of filtering, according to claim 15, further including the step of providing means for sampling the recovered input signal at a reduced rate after it is filtered by said second d-igital filter means.
Claim 22
Dependent Claim
31 words
The method of filtering, according to claim 15, wherein the step of providing said first N-order decimating FIR digital filter means includes sampling the recovered input signal at a reduced rate.
Claim 23
Dependent Claim
37 words
The method of filtering, according to claim 15, further including the step of latching, through a plurality of latches clocked by said first clock, to sequentially latch data to said first N-order decimating FIR digital filter means.
Claim 24
Dependent Claim
22 words
The method of filtering, according to claim 21, wherein said first N-order decimating FIR digital filter means includes an N-order FIR filter.
Claim 25
Dependent Claim
35 words
The method of filtering, according to claim 22, wherein said N-order decimating FIR filter means includes a plurality of latches, clocked by said second clock means, for sequentially latching data from the recovered input signal.
Claim 26
Dependent Claim
39 words
The method of filtering, according to claim 23, wherein said N-order decimating FIR filter includes at least one additional latch, clocked by said second clock means, for sequentially latching data from selected ones of said second plurality of latches.
Claim 27
Dependent Claim
31 words
The method of filtering, accordirg to claim 22, wherein said N-order decimating FIR filter includes means for multiplying coefficients corresponding to a predetermined filtering algorithm of said N-order decimating FIR filter.
Claim 28
Dependent Claim
27 words
The method of filtering, according to claim 22, wherein said N-order decimating FIR filter includes means for adding decimated samples to generate a band-limited recovered input signal.
References Cited (Backward Citations)
US3303335A
Cited
DE2158378A1
Cited
US3979701A
Cited
US4057759A
Cited
US4455680A
Cited
US4346477A
Cited
US4246653A
Cited
US4313211A
Cited
GB2081047A
Cited
US4356559A
Cited
US4419759A
Cited
US4384357A
Cited
US4589110A
Cited
US4623922A
Cited
US4559499A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |