US4729963A
Expired / Lapsed
US
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Fabrication method for modified planar semiconductor structures
Assignee: STANFORD UNIVERSITY OTL LLC
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Filing: 1986-11-21
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Granted: 1988-03-08
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Expires: 2006-11-21
Abstract
Abstract A process for fabricating a semiconductor device or a semiconductor substrate having a first major surface on which active semiconductor devices are to be formed, and a second major surface. An etch stop layer is provided on the first major surface. A layer of semiconductor material is deposited on the etch stop layer and portions of the substrate are selectively removed to provide a pattern of apertures in the layer extending to the etch stop layer. Dopant species are provided through the second major surface to form active regions in the layer of semiconductor material.
Inventors
- 👤 Nader Tabatabaie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:56
CPC Classifications
G; G02; G02B; G02B6/00; G02B6/24; G02B6/42; G02B6/4201; G02B6/4219; G02B6/4228; G02B6/423; G02B6/4202; H; H10; H10F; H10F30/00; H10F30/20; H10F30/21; H10F30/22; H10F30/225; H10F30/2255; H10F39/00; H10F39/10; H10F39/103; H10F71/00; H10F71/127; H10F71/1272; Y; Y02; Y02E; Y02E10/00; Y02E10/50; Y02E10/544; Y02P; Y02P70/00; Y02P70/50
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
118 words
A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate having a first major surface on which active semiconductor devices are to be formed, and a second major surface; providing an epitaxially grown etch stop first layer on said first major surface; epitaxially depositing a second layer composed of semiconductor material on said etch stop layer; depositing a third layer composed of semiconductor material on said second layer of semiconductor material selectively removing portions of said semiconductor substrate to provide a pattern of apertures in said substrate extending to said etch stop layer; and providing a dopant species through said second surface to form active regions in said second layer of semiconductor material.
Claim 2
Dependent Claim
118 words
A process for fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate having a first major surface on which active semiconductor devices are to be formed, and a second major surface; providing an epitaxially grown etch stop first layer on said first major surface; epitaxially depositing a second layer composed of semiconductor material on said etch stop layer; depositing a third layer composed of semiconductor material on said second layer of semiconductor material selectively removing portions of said semiconductor substrate to provide a pattern of apertures in said substrate extending to said etch stop layer; and providing a dopant species through said second surface to form active regions in said second layer of semiconductor material.
Claim 3
Dependent Claim
19 words
A process as defined in claim 1, wherein said step of selectively removing protions of said semiconductor stbstrate comprises
Claim 4
Dependent Claim
30 words
applying a masking layer to said subsrate to define a pattern thereon; and etching through the unmasked portions of said substrate to define a pattern of apertures in said substrate.
Claim 5
Dependent Claim
30 words
applying a masking layer to said subsrate to define a pattern thereon; and etching through the unmasked portions of said substrate to define a pattern of apertures in said substrate.
Claim 6
Dependent Claim
36 words
A process as defined in claim 2, wherein said step of etching comprises immersing said substrate in a 1% etching solution of Br in methanol, followed by immersing said substrate in an etching solution of HCl.
Claim 7
Dependent Claim
12 words
A process as defined in claim 1 wherein said substrate is semi-insulating.
Claim 8
Dependent Claim
12 words
A process as defined in claim 4, wherein said substrate is Fe:InP.
Claim 9
Dependent Claim
14 words
A process as defined in claim 1, wherein said etch stop layer is InGaAsP.
Claim 10
Dependent Claim
17 words
A process as defined in claim 1 wherein said second layer composed of semiconductor material comprises InP.
Claim 11
Dependent Claim
15 words
A process as defined in claim 1, wherein said third layer is comprosed of InGaAs.
Claim 12
Dependent Claim
26 words
A process as defined in claim 1, further comprising the step of depositing a fourth layer of semiconductor material on said third layer of semiconductor material.
Claim 13
Dependent Claim
17 words
A process as deined in claim 9, wherein said fourth layer is composed of heavily doped InGaAs.
Claim 14
Dependent Claim
22 words
A process as defined in claim 1, wherein said step of providing a dopant species through said second layer comprises Zn diffusion.
Claim 15
Dependent Claim
19 words
A process as defined in claim 1, wherein the semiconductor device fabricated therein is a junction field effect transistor.
References Cited (Backward Citations)
US3593067A
Cited
US3849678A
Cited
US3604987A
Cited
US3617823A
Cited
US3689900A
Cited
US3735137A
Cited
US3792258A
Cited
US4143269A
Cited
US4142207A
Cited
US4416053A
Cited
US4547792A
Cited
US4354898A
Cited
US4534033A
Cited
US4566171A
Cited
US4507845A
Cited
US4537654A
Cited
US4660208A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-08 | 1991-09-07 | 1992-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-08 | 1995-09-07 | 1996-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-08 | 1999-09-07 | 2000-03-08 | $7700.00 | Window Closed / Lapsed |