Selective access array integrated circuit

Claim 2

A selective access array integrated circuit comprising: a common body of semiconductor material having a first and a second major surface; a plurality of electronic devices implemented in a first array on said first major surface, each one of said electronic devices capable of transferring information which changes over a period of time; a plurality of electronic access elements implemented in a second array, each access element corresponding to at least one of said electronic devices in said first array; a plurality of signal output pads disposed on the periphery of said second major surface of said body for connection to corresponding respective ones of said electronic devices for simultaneous receiving data from said ones of electronic devices and simultaneously transferring such data externally of said circuit in a non-sequential, parallel data manner, and access means connected to electronic access elements for selectively providing an access signal for continuously and simultaneously accessing predetermined ones of said electronic devices, and forming and maintaining a plurality of electrical readout paths from a selectively determined plurality of ones of said electronic devices to respective ones of said output pads for a predetermined period of time which is independent of any internal operative characteristic of said array circuit.

Claim 3

A circuit as defined in claim 1, wherein said access elements are disposed on said second major surface in an array of parallel rows and parallel columns, the rows being disposed perpendicular to the columns, and further comprising conductive bus lines interconnecting said access elements for forming respective ones of said electrical readout path through ones of said access elements which have been activated by said access means from ones of said electronic devices to respective ones of said signal output pads.

Claim 4

A circuit as defined in claim 1 wherein said plurality of electronic devices are substantially identical infrared radiation detectors, and each of said electronic access elements comprise a pair of MOS field effect transistors.

Claim 5

A circuit as defined in claim 1 wherein said access means comprise X-address select means and Y-address select means which together function to select ones of said electronic access elements.

Claim 6

A circuit as defined in claim 4, wherein each electronic access element comprises: a first field effect transistor having a first and second conduction path electrodes and a control electrode, said first conduction path electrodes being connected to said Y-address select means, and said control electrode connected to said X-address select means; and a second field effect transistor having a first conduction path electrode connected to said electronic device, a second conduction path electrode connected to an output, and a control electrode connected to said second conduction path electrode of said first field effect transistor.

Claim 7

A selective access array integrated circuit comprising: a common body of semiconductor material having a first and a second major surface; a plurality of substantially identical electronic devices implemented in a first array on said first major surface; a plurality of electronic access devices implemented in a second array on said second major surface, each access device corresponding to at least one of said electronic devices in said first array; a plurality of signal output pads on said body for connection to corresponding respective ones of said electronic devices for simultaneous receiving data from said ones of electronic devices and only transferring such data externally of said circuit in a non-sequential, parallel data manner; and access means implemented on said second major surface and connected to electronic access devices for selectively and simultaneously providing access signals to selected ones of said access devices for accessing a predetermined plurality of said electronic devices, and forming and maintaining an plurality of independent, electrically isolated electrical readout paths through groups of selected ones of said access devices, each of said groups forming a single readout path from one of said electronic devices to a respective output pad, said readout path being maintained for a predetermined period of time independent of any internal characteristic of said array circuit so that data is read continuously from each of said predetermined plurality of electronic devices to said respective output pads.

Claim 8

A selective access array integrated circuit comprising: a common body of semiconductor material having a first and a second major surface; a plurality of substantially identical electronic devices implemented in a first array on said first major surface; a plurality of electronic access devices implemented in a second array on said second major surface, each access device corresponding to at least one of said electronic devices in said first array; a plurality of signal output pads on said body for connection to corresponding respective ones of said electronic devices for simultaneous receiving data from said ones of electronic devices and only transferring such data externally of said circuit in a non-sequential, parallel data manner; and access means implemented on said second major surface and connected to electronic access devices for selectively and simultaneously providing access signals to selected ones of said access devices for accessing a predetermined plurality of said electronic devices, and forming and maintaining an plurality of independent, electrically isolated electrical readout paths through groups of selected ones of said access devices, each of said groups forming a single readout path from one of said electronic devices to a respective output pad, said readout path being maintained for a predetermined period of time independent of any internal characteristic of said array circuit so that data is read continuously from each of said predetermined plurality of electronic devices to said respective output pads.

Claim 9

A solid state image sensor comprising: a common body of semiconductor material having a first and a second major surface; a plurality of substantially identical radiation sensitive electronic devices implemented in a first array on said first major surface comprising a layer of aluminum over a surface portion of the first major surface, and a heavily doped impurity layer in window aperture areas of said first major surface where the aluminum layer is absent and said radiation sensitive devices are formed; an n-type epitaxial layer implemented on said second major surface including a plurality of electronic access elements implemented in a second array, each element including a pair of MOS field effect transistors, each access element corresponding to at least one of said electronic devices in said first array; an identation in said second major surface for permitting an electrode of one of said MOS field effect transistors to make electrical contact with said common body of semiconductor material in a region directly beneath a window aperture of said first major surface and the corresponding radiation sensitive device; and access means implemented on said second major surface and connected to said electronic access elements for selectively and simultaneously providing access signals during a first time period for continuously accessing a predetermined plurality of said electronic devices; and for providing access signals during a second subsequent time period for continuously accessing a second predetermined plurality of said electronic devices, an electrical readout path being established and maintained simultaneously from a selectively determined plurality of ones of said electronic devices to corresponding outputs for a period of time determined independently of any characteristic of the sensor.

Claim 10

A solid state image sensor comprising: a common body of semiconductor material having a first and a second major surface; a plurality of substantially identical radiation sensitive electronic devices implemented in a first array on said first major surface comprising a layer of aluminum over a surface portion of the first major surface, and a heavily doped impurity layer in window aperture areas of said first major surface where the aluminum layer is absent and said radiation sensitive devices are formed; an n-type epitaxial layer implemented on said second major surface including a plurality of electronic access elements implemented in a second array, each element including a pair of MOS field effect transistors, each access element corresponding to at least one of said electronic devices in said first array; an identation in said second major surface for permitting an electrode of one of said MOS field effect transistors to make electrical contact with said common body of semiconductor material in a region directly beneath a window aperture of said first major surface and the corresponding radiation sensitive device; and access means implemented on said second major surface and connected to said electronic access elements for selectively and simultaneously providing access signals during a first time period for continuously accessing a predetermined plurality of said electronic devices; and for providing access signals during a second subsequent time period for continuously accessing a second predetermined plurality of said electronic devices, an electrical readout path being established and maintained simultaneously from a selectively determined plurality of ones of said electronic devices to corresponding outputs for a period of time determined independently of any characteristic of the sensor.

Claim 11

A selective access array integrated circuit comprising: a common body of semiconductor material having a first and a second major surface; a plurality of electronic devices implemented in a first array on said first major surface, each one of said electronic devices capable of transferring information which changes over a period of time; a plurality of electronic access devices implemented in a second array, each access device corresponding to at least one of said electronic devices in said first array; a plurality of signal output pads disposed on the periphery of said body for connection to corresponding respective ones of said electronic devices for simultaneous receiving data from said ones of electronic devices and transferring such data externally of said circuit; and access means connected to electronic access devices for selectively providing an access signal for continuously and simultaneously accessing predetermined ones of said electronic devices, and forming and maintaining an electrical readout path a selectively determined plurality of ones of said electronic devices to corresponding output pads for a predetermined period of time independent of any internal operative characteristic of said array circuit, said access means comprises X-address select lines, and Y-address select lines, an X-address and a Y-address line together functioning to activate ones of said electronic access devices, and bus means for providing continuous and simultaneous access to said predetermined ones of said electronic devices; characterized in that said electronic access devices comprise a first field effect transistor having first and second conduction path electrodes and a control electrode; said first conduction path electrode being connected to said Y-address select lines, and said control electrode connected to said X-address select lines; and a second field effect transistor having a first conduction path electrode connected to said electronic device, a second conduction path electrode connected to an output line extending across said second major surface to the periphery of said second major surface, and a control electrode connected to said second conduction path electrode of said first field effect transistor, said output line connected to one of said signal output pads, such that when one of said Y-address select lines and one of said X-address select lines is activated, said first and said second transistors are turned on, and information from said corresponding electronic device being transferred continuously through said second field effect transistor to said respective signal output pad.

Claim 12

A selective access array integrated circuit comprising: a common body of semiconductor material having a first and a second major surface; a plurality of electronic devices implemented in a first array on said first major surface, each one of said electronic devices capable of transferring information which changes over a period of time; a plurality of electronic access devices implemented in a second array, each access device corresponding to at least one of said electronic devices in said first array; a plurality of signal output pads disposed on the periphery of said body for connection to corresponding respective ones of said electronic devices for simultaneous receiving data from said ones of electronic devices and transferring such data externally of said circuit; and access means connected to electronic access devices for selectively providing an access signal for continuously and simultaneously accessing predetermined ones of said electronic devices, and forming and maintaining an electrical readout path a selectively determined plurality of ones of said electronic devices to corresponding output pads for a predetermined period of time independent of any internal operative characteristic of said array circuit, said access means comprises X-address select lines, and Y-address select lines, an X-address and a Y-address line together functioning to activate ones of said electronic access devices, and bus means for providing continuous and simultaneous access to said predetermined ones of said electronic devices; characterized in that said electronic access devices comprise a first field effect transistor having first and second conduction path electrodes and a control electrode; said first conduction path electrode being connected to said Y-address select lines, and said control electrode connected to said X-address select lines; and a second field effect transistor having a first conduction path electrode connected to said electronic device, a second conduction path electrode connected to an output line extending across said second major surface to the periphery of said second major surface, and a control electrode connected to said second conduction path electrode of said first field effect transistor, said output line connected to one of said signal output pads, such that when one of said Y-address select lines and one of said X-address select lines is activated, said first and said second transistors are turned on, and information from said corresponding electronic device being transferred continuously through said second field effect transistor to said respective signal output pad.

Claim 13

A selective access solid state sensor array integrated circuit comprising: a common body of semiconductor material having a first and a second major surface; a plurality of substantially identical electronic sensor devices implemented in a first array on said first major surface; a plurality of electronic access devices implemented in a second array on said second major surface, each access device corresponding to at least one of said electronic sensor devices in said first array; a plurality of signal output pads on said second major surface of said body for connection to corresponding respective ones of said electronic sensor devices for simultaneous receiving data from said ones of electronic sensor devices and transferring such data externally of said circuit in a non-sequential, parallel data manner, and access means implemented on said second major surface and connected to electronic access devices for selectively and simultaneously providing access signals for accessing a predetermined plurality of said electronic sensor devices, which, when operable at cryogenic temperatures, form and maintain a plurality of continuous electrical readout paths from a selectively determined plurality of ones of said electronic sensor devices to corresponding respective ones of said output pads for a predetermined period of time which is independent of any internal characteristic of said array circuit.

Claim 14

A selective access solid state sensor array integrated circuit comprising: a common body of semiconductor material having a first and a second major surface; a plurality of substantially identical electronic sensor devices implemented in a first array on said first major surface; a plurality of electronic access devices implemented in a second array on said second major surface, each access device corresponding to at least one of said electronic sensor devices in said first array; a plurality of signal output pads on said second major surface of said body for connection to corresponding respective ones of said electronic sensor devices for simultaneous receiving data from said ones of electronic sensor devices and transferring such data externally of said circuit in a non-sequential, parallel data manner, and access means implemented on said second major surface and connected to electronic access devices for selectively and simultaneously providing access signals for accessing a predetermined plurality of said electronic sensor devices, which, when operable at cryogenic temperatures, form and maintain a plurality of continuous electrical readout paths from a selectively determined plurality of ones of said electronic sensor devices to corresponding respective ones of said output pads for a predetermined period of time which is independent of any internal characteristic of said array circuit.