Patent US4725984A successfully refreshed from Google Patents.
US4725984A
Expired / Lapsed
US
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CMOS eprom sense amplifier
Assignee: Atmel Corp
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Filing: 1984-02-21
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Granted: 1988-02-16
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Expires: 2004-02-21
Abstract
Abstract Individual CMOS floating-gate memory cells capable of storing data are arranged in an array structure and selected with horizontal and vertical access lines. Current flow through the array cells is measured, amplified, and then compared with an unprogrammed cell using the sense amplifier of the present invention. The sense amplifier tolerates increased variation in the characteristics of programmed or unprogrammed cells and therefore increases the manufacturing yields of the arrays. It additionally achieves fast accessing and sensing of the stored data.
Inventors
- 👤 William W. Ip
- 👤 Gust Perlegos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:55
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
180 words
A circuit for sensing a memory cell value, comprising: (a) a first floating gate transistor programmed with a memory data value, whose gate is electrically connected to a select line and whose drain is electrically connected to ground; (b) a first field effect transistor whose gate and drain are electrically connected to the source of said first floating gate transistor and whose source is electrically connected to a voltage source; (c) a second floating gate transistor programmed with a reference data value, whose gate is electrically connected to the gate of the first floating gate transistor and whose drain is electrically connected to ground; (d) a second field effect transistor whose gate is electrically connected to the gate of said first field effect transistor and whose source is electrically connected to a voltage source and whose drain is electrically connected to the source of said second floating gate transistor; whereby the voltage appearing at the node between said second floating gate transistor and said second field effect transistor is indicative of the data stored in said first floating gate transistor.
Claim 2
Dependent Claim
180 words
A circuit for sensing a memory cell value, comprising: (a) a first floating gate transistor programmed with a memory data value, whose gate is electrically connected to a select line and whose drain is electrically connected to ground; (b) a first field effect transistor whose gate and drain are electrically connected to the source of said first floating gate transistor and whose source is electrically connected to a voltage source; (c) a second floating gate transistor programmed with a reference data value, whose gate is electrically connected to the gate of the first floating gate transistor and whose drain is electrically connected to ground; (d) a second field effect transistor whose gate is electrically connected to the gate of said first field effect transistor and whose source is electrically connected to a voltage source and whose drain is electrically connected to the source of said second floating gate transistor; whereby the voltage appearing at the node between said second floating gate transistor and said second field effect transistor is indicative of the data stored in said first floating gate transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |