Patent US4724340A successfully refreshed from Google Patents.
US4724340A
Expired / Lapsed
US
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Output circuit in which induced switching noise is reduced by presetting pairs of output lines to opposite logic states
Assignee: Motorola Solutions Inc
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Filing: 1986-11-21
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Granted: 1988-02-09
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Expires: 2006-11-21
Abstract
Abstract An integrated circuit has a plurality of outputs which switch to a valid condition at the same time. Because integrated circuits have leads for power supply terminals, there is inductance on these leads. When an output switches logic states, there is a change in current flow so that there is a voltage drop across the inductive lead which is used for power supply coupling. This voltage drop, expressed Ldi/dt, is proportional to the number of outputs which are switched. The worst case for the positive power supply terminal Ldi/dt is when all of the outputs switch from a logic low to a logic high. This worst case is reduced in half by predisposing half of the outputs to one logic state and the other half to the other logic state. This also reduces the worst case for the negative power supply terminal, frequently ground, in half which is the case when all of the outputs switch from a logic high to a logic low.
Inventors
- 👤 Lal C. Sood
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:46
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
142 words
In an integrated circuit having a first output terminal and a second output terminal, a circuit comprising: first buffer means for providing a first output signal on the first output terminal at one of two possible logic states in response to a control signal, said logic state provided being indicative of a first input signal; second buffer means for providing a second output signal on the second output terminal at one of the two possible logic states in response to the control signal, said logic state provided being indicative of a second input signal; and predisposition means, coupled to the first and second outputs, for causing the first and second outputs to be at different logic states at least immediately prior to the first and second buffer means providing the first and second output signals on the first and second output terminals.
Claim 2
Dependent Claim
142 words
In an integrated circuit having a first output terminal and a second output terminal, a circuit comprising: first buffer means for providing a first output signal on the first output terminal at one of two possible logic states in response to a control signal, said logic state provided being indicative of a first input signal; second buffer means for providing a second output signal on the second output terminal at one of the two possible logic states in response to the control signal, said logic state provided being indicative of a second input signal; and predisposition means, coupled to the first and second outputs, for causing the first and second outputs to be at different logic states at least immediately prior to the first and second buffer means providing the first and second output signals on the first and second output terminals.
Claim 3
Dependent Claim
108 words
The integrated circuit of claim 1, wherein the predisposition means is further characterized as detecting the logic states of the first and second output terminals and changing the logic state on the first output terminal if both the first and second output terminals are detected as being at a first logic state, changing the logic state on the second output terminal if both the first and second output terminals are detected as being at a second logic state, and not changing the logic state on either the first or second output terminal if the logic states of the first and second output terminals are detected as being different.
Claim 4
Dependent Claim
36 words
The integrated circuit of claim 2 further characterized as being a memory which provides data in response to an address further comprising: address detection means for providing the control signal in response to an address transition.
Claim 5
Dependent Claim
57 words
The integrated circuit of claim 3 wherein: the address detection means is further characterized as providing a predisposition signal to the predisposition means prior to providing the control signal; and the predisposition means is further characterized as causing the first and second output terminals to be at different logic states in response to receiving the predisposition signal.
Claim 6
Dependent Claim
32 words
The integrated circuit of claim 4 wherein the predisposition means is further characterized as providing a set signal for causing the first and second output terminals to be at different logic states.
Claim 7
Dependent Claim
59 words
The integrated circuit of claim 5 wherein the predisposition means is further characterized as providing the set signal in response to the predisposition signal when both the first and second output terminals are detected as being at a first logic state or when both the first and second output terminals are detected as being at a second logic state.
Claim 8
Dependent Claim
46 words
The integrated circuit of claim 6 wherein: the first buffer means is further characterized as providing coupling between the first output terminal and the set signal; and the second buffer means is further characterized as providing coupling between the second output terminal and the set signal.
Claim 9
Dependent Claim
54 words
The integrated circuit of claim 7 wherein: the first buffer is further characterized as providing the second logic state on the first output terminal in response to the set signal; and the second buffer is further characterized as providing the first logic state on the second output terminal in response to the set signal.
Claim 10
Dependent Claim
46 words
The integrated circuit of claim 1 wherein: the first buffer means is further characterized as providing coupling between the first output terminal and the prediposition means; and the second buffer means is further characterized as providing coupling between the second output terminal and the predisposition means.
Claim 11
Dependent Claim
36 words
The integrated circuit of claim 1 further characterized as being a memory which provides data in response to an address, further comprising: address detection means for providing the control signal in response to an address transition.
Claim 12
Dependent Claim
57 words
The integrated circuit of claim 10 wherein: the address detection means is further characterized as providing a predisposition signal to the predisposition means prior to providing the control signal; and the predisposition means is further characterized as causing the first and second output terminals to be at different logic states in response to receiving the predisposition signal.
Claim 13
Dependent Claim
32 words
The integrated circuit of claim 1 wherein the predisposition means is further characterized as providing a set signal for causing the first and second output terminals to be at different logic states.
Claim 14
Dependent Claim
59 words
The integrated circuit of claim 12 wherein the predisposition means is further characterized as providing the set signal in response to the predisposition signal when both the first and second output terminals are detected as being at a first logic state or when both the first and second output terminals are detected as being at a second logic state.
Claim 15
Dependent Claim
126 words
In an integrated circuit having a first output terminal and a second output terminal, a method comprising the steps of: providing a first output signal on the first output terminal at one of two possible logic states in response to a control signal, said logic state provided being indicative of a first input signal; providing a second output signal on the second output terminal at one of the two possible logic states in response to the control signal, said logic state provided being indicative of a second input signal; and causing the first and second outputs to be at different logic states at least immediately prior to the first and second buffer means providing the first and second output signals on the first and second outputs.
Claim 16
Dependent Claim
126 words
In an integrated circuit having a first output terminal and a second output terminal, a method comprising the steps of: providing a first output signal on the first output terminal at one of two possible logic states in response to a control signal, said logic state provided being indicative of a first input signal; providing a second output signal on the second output terminal at one of the two possible logic states in response to the control signal, said logic state provided being indicative of a second input signal; and causing the first and second outputs to be at different logic states at least immediately prior to the first and second buffer means providing the first and second output signals on the first and second outputs.
Claim 17
Dependent Claim
29 words
The method of claim 14 further comprising the step of: detecting the logic states of the first and second output terminals prior to the occurrence of the control signal.
Claim 18
Dependent Claim
38 words
The method of claim 15 further comprising the step of forcing the first output terminal to a different logic state if both of the first and second output terminals are detected as being at a first logic state.
Claim 19
Dependent Claim
38 words
The method of claim 16 further comprising the step of forcing the second output terminal to a different logic state if both of the first and second output terminals are detected as being at a second logic state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-08 | 1991-08-10 | 1992-02-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-08 | 1995-08-10 | 1996-02-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-08 | 1999-08-10 | 2000-02-09 | $7700.00 | Window Closed / Lapsed |