US4633102A
Expired / Lapsed
US
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High speed address transition detector circuit for dynamic read/write memory
Assignee: Texas Instruments Inc
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Filing: 1984-07-09
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Granted: 1986-12-30
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Expires: 2004-07-09
Abstract
Abstract A transition of an address input of a memory device is detected in a CMOS circuit having a pair of AND gates Or'ed together. One AND gate receives the input bit and a delayed complement of this bit. The other AND gate receives the complement of the input bit and a delayed version of the true bit. The delays are RC circuits with time constants longer than the transition times. The output of the gates uses a pull-up device to restore a zero level after each transition is indicated. A number of these transition detectors may be OR'ed together to monitor all of the address bits of a memory device.
Inventors
- 👤 Jimmie D. Childers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:51
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; H; H03; H03K; H03K5/00; H03K5/153; H03K5/1534
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
250 words
A transition detector circuit comprising: an input terminal, and an inverter having an input connected to said input terminal and producing an inverted input; an output node, and a pull-up resistance connecting said output node to a voltage supply; a first logic circuit having first and second transistors each including a gate and a source-to-drain path, said source-to-drain paths connected in series and the series-connected source-to-drain paths connected between said output node and reference potential; means connecting said gate of the first transistor to said input terminal; and a first delay circuit coupling said gate of the second transistor to said input terminal; a second logic circuit having third and fourth transistors each including a gate and a source-to-drain path, said source-to-drain paths of the third and fourth transistors connected in series and the series-connected source-to-drain paths connected between said output node and reference potential; means connecting said gate of the third transistor to said inverted input; and a second delay circuit coupling said gate of the fourth transistor to said inverted input, wherein each of said first and second delay circuits comprises a P-channel transistor and an N-channel transistor, each having a source-to-drain path and a gate, the source-to-drain paths being connected in series across a voltage supply, the gates being connected together to input of the respective delay circuit, and juncture of the source-to-drain paths connected to an output of the respective delay circuit and a capacitor connected in parallel with the source-to-drain path of the N-channel transistor.
Claim 2
Dependent Claim
250 words
A transition detector circuit comprising: an input terminal, and an inverter having an input connected to said input terminal and producing an inverted input; an output node, and a pull-up resistance connecting said output node to a voltage supply; a first logic circuit having first and second transistors each including a gate and a source-to-drain path, said source-to-drain paths connected in series and the series-connected source-to-drain paths connected between said output node and reference potential; means connecting said gate of the first transistor to said input terminal; and a first delay circuit coupling said gate of the second transistor to said input terminal; a second logic circuit having third and fourth transistors each including a gate and a source-to-drain path, said source-to-drain paths of the third and fourth transistors connected in series and the series-connected source-to-drain paths connected between said output node and reference potential; means connecting said gate of the third transistor to said inverted input; and a second delay circuit coupling said gate of the fourth transistor to said inverted input, wherein each of said first and second delay circuits comprises a P-channel transistor and an N-channel transistor, each having a source-to-drain path and a gate, the source-to-drain paths being connected in series across a voltage supply, the gates being connected together to input of the respective delay circuit, and juncture of the source-to-drain paths connected to an output of the respective delay circuit and a capacitor connected in parallel with the source-to-drain path of the N-channel transistor.
Claim 3
Dependent Claim
35 words
A circuit according to claim 1 wherein each said N-channel transistors has a size selected to provide a resistance for an RC delay, and said capacitors are selected to provide capacitance of such RC delay.
Claim 4
Dependent Claim
24 words
A circuit according to claim 1 wherein said first, second, third and fourth transistors are N-channel, and said pull-up resistance is a P-channel transistor.
Claim 5
Dependent Claim
295 words
A transition detector circuit for a CMOS memory device or the like, comprising: an input terminal, and a CMOS inverter having an input connected to said input terminal and producing an inverted input; an output node, and a P-channel pull-up transistor connecting said output node to a positive voltage supply; a first logic circuit having first and second N-channel transistors, each of said first and second transistors having a gate and a source-to-drain path, said source-to-drain paths connected in series and the series-connected source-to-drain paths connected between said output node and ground; means connecting said gate of the first transistor to said input terminal; and a first inverting delay circuit connecting the gate of the second transistor to said input terminal; a second logic circuit having third and fourth N-channel transistors, each of said third and fourth transistors having a gate and a source-to-drain path, said source-to-drain paths connected in series and the series-connected source-to-drain paths of the third and fourth transistors connected between said output node and ground; means connecting said gate of the third transistor to said inverted input; and a second inverting delay circuit connecting said gate of the fourth transistor to said inverted input; wherein each of said first and second inverting delay circuits comprises a P-channel transistor and an N-channel transistor each having a source-to-drain path and a gate, the source-to-drain paths of said P-channel and N-channel transistors being connected in series across said voltage supply, the gates of said P-channel and N-channel transistors being connected together to input of the respective delay circuit, and juncture of the source-to-drain paths of said P-channel and N-channel transistors being connected to an output of the respective delay circuit and a capacitor connected in parallel with the source-to-drain path of the N-channel transistor.
Claim 6
Dependent Claim
295 words
A transition detector circuit for a CMOS memory device or the like, comprising: an input terminal, and a CMOS inverter having an input connected to said input terminal and producing an inverted input; an output node, and a P-channel pull-up transistor connecting said output node to a positive voltage supply; a first logic circuit having first and second N-channel transistors, each of said first and second transistors having a gate and a source-to-drain path, said source-to-drain paths connected in series and the series-connected source-to-drain paths connected between said output node and ground; means connecting said gate of the first transistor to said input terminal; and a first inverting delay circuit connecting the gate of the second transistor to said input terminal; a second logic circuit having third and fourth N-channel transistors, each of said third and fourth transistors having a gate and a source-to-drain path, said source-to-drain paths connected in series and the series-connected source-to-drain paths of the third and fourth transistors connected between said output node and ground; means connecting said gate of the third transistor to said inverted input; and a second inverting delay circuit connecting said gate of the fourth transistor to said inverted input; wherein each of said first and second inverting delay circuits comprises a P-channel transistor and an N-channel transistor each having a source-to-drain path and a gate, the source-to-drain paths of said P-channel and N-channel transistors being connected in series across said voltage supply, the gates of said P-channel and N-channel transistors being connected together to input of the respective delay circuit, and juncture of the source-to-drain paths of said P-channel and N-channel transistors being connected to an output of the respective delay circuit and a capacitor connected in parallel with the source-to-drain path of the N-channel transistor.
Claim 7
Dependent Claim
35 words
A circuit according to claim 4 wherein each said N-channel transistor has a size selected to provide a resistance for an RC delay, and said capacitors are selected to provide capacitance of such RC delay.
Claim 8
Dependent Claim
21 words
A circuit according to claim 4 wherein a plurality of said detector circuits are connected with said output nodes in common;
Claim 9
Dependent Claim
26 words
A circuit according to claim 6 wherein address input bits for a memory device are connected to said input terminals of the plurality of detector circuits.
References Cited (Backward Citations)
US4286174A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |