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US4719600A
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Sense circuit for multilevel storage system
Assignee: International Business Machines Corp
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Filing: 1986-02-18
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Granted: 1988-01-12
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Expires: 2006-02-18
Abstract
Abstract An improved sense circuit for determining the data state of a memory cell in a multilevel storage system is disclosed. The sense circuit includes at least two differential voltage level sensing circuits. A first differential voltage level sensing circuit compares the relative magnitudes of a data input signal voltage level corresponding to a particular memory cell charge level and a first reference voltage level, thereby providing at least one first binary data output signal. The first binary data output signal is then used to generate a second reference voltage level having a magnitude different from that of the first reference voltage level. A second differential voltage sensing level circuit compares the relative magnitudes of an adjusted data input signal voltage level and a second reference voltage level, thereby providing at least one second binary data output signal. The adjusted data input signal corresponds to a function of the first data input signal. Hence, the binary data output signals provided correspond to the charge level stored in the memory cell.
Inventors
- 👤 David R. Huffman
- 👤 Scott C. Lewis
- 👤 James E. Rock
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/565; G11C27/00; G11C27/02; G11C27/024; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
297 words
A sense circuit for determining the data state of a data input signal corresponding to one of n charges levels, comprising: means for providing a data input signal voltage level representing a data state corresponding to one of n charge levels, n being an integer greater than 2; means for generating a first reference voltage having a predetermined level of magnitude; a first differential voltage level sensing circuit responsive to said data input signal voltage level and to said first reference voltage level, said first differential voltlage level sensing circuit providing at least one first binary data output signal as a function of the relative magnitudes of said data input signal voltage level and said first reference voltage level; means responsive to said first binary data output and said data input signal voltage level for generating an adjusted data signal voltage having a magnitude corresponding to a function of said data input signal voltage level and said first binary data output signal; means responsive to said first binary data output signal for generating a second reference voltage having a level of magnitude different from that of said first reference voltage level; and a second differential voltage level sensing circuit responsive to an adjusted data input signal voltage level and to said second reference voltage level, said second differential voltage level sensing circuit providing at least one second binary data output signal as a function of the relative magnitudes of said adjusted data input signal voltage level and said second reference voltage level; means responsive to said first binary data output signal and said second binary data output signal for determining the data state of one of said n charge levels as a function of said first binary data output signal and said second binary data output signal.
Claim 2
Dependent Claim
297 words
A sense circuit for determining the data state of a data input signal corresponding to one of n charges levels, comprising: means for providing a data input signal voltage level representing a data state corresponding to one of n charge levels, n being an integer greater than 2; means for generating a first reference voltage having a predetermined level of magnitude; a first differential voltage level sensing circuit responsive to said data input signal voltage level and to said first reference voltage level, said first differential voltlage level sensing circuit providing at least one first binary data output signal as a function of the relative magnitudes of said data input signal voltage level and said first reference voltage level; means responsive to said first binary data output and said data input signal voltage level for generating an adjusted data signal voltage having a magnitude corresponding to a function of said data input signal voltage level and said first binary data output signal; means responsive to said first binary data output signal for generating a second reference voltage having a level of magnitude different from that of said first reference voltage level; and a second differential voltage level sensing circuit responsive to an adjusted data input signal voltage level and to said second reference voltage level, said second differential voltage level sensing circuit providing at least one second binary data output signal as a function of the relative magnitudes of said adjusted data input signal voltage level and said second reference voltage level; means responsive to said first binary data output signal and said second binary data output signal for determining the data state of one of said n charge levels as a function of said first binary data output signal and said second binary data output signal.
Claim 3
Dependent Claim
91 words
The sense circuit of claim 1 wherein said means responsive to said first binary data output signal for generating a second reference voltage level comprises: at least one capacitor having one terminal connected to said first binary data outpout signal of said first differential voltage level sensing circuit; and at least one transistor connected between an internal sense node of said second differential voltage sensing circuit for said second reference voltage level and the other terminal of said capacitor, the gate electrode of said transistor connected to a clocked voltage signal.
Claim 4
Dependent Claim
23 words
The sense circuit of claim 2 wherein said first and second differential voltage level sensing circuits each comprise a cross-coupled sense amplifier circuit.
Claim 5
Dependent Claim
23 words
The sense circuit of claim 1 further comprising a re-write circuit connected between said first and said second differential voltage level sensing circuits.
Claim 6
Dependent Claim
23 words
The sense circuit of claim 4 wherein said first and second differential voltage level sensing circuits each comprise a cross-coupled sense amplifier circuit.
Claim 7
Dependent Claim
23 words
The sense circuit of claim 1 wherein said first and second differential voltage level sensing circuits each comprise a cross-coupled sense amplifier circuit.
Claim 8
Dependent Claim
99 words
The sense circuit of claim 1 wherein said means responsive to said first binary data output and said data input signal voltage level for generating an adjusted data signal voltage level comprises: at least one capacitor having one terminal connected to said first binary data output signal of said first differential voltage level sensing circuit; and at least one transistor connected between an internal sense node of said second differential voltage sensing circuit for said adjusted data signal voltage level and the other terminal of said capacitor, the gate electrode of said transistor connected to a clocked voltage signal.
Claim 9
Dependent Claim
23 words
The sense circuit of claim 7 wherein said first and second differential voltage level sensing circuits each comprise a cross-coupled sense amplifier circuit.
Claim 10
Dependent Claim
133 words
The sense circuit of claim 1 wherein said means responsive to said first binary data output signal and said second binary data output signal for determining the data state of said n charge level comprises: at least one transistor with a first end connected to the first binary output signal of said first differential voltage level sensing circuit and a second end providing the first binary data output signal when the gate electrode of said transistor is pulsed with a clocked voltage signal; and at least one transistor with a first end connected to the second binary data output signal of said second differential voltage level sensing circuit and a second end providing the second binary data output signal when the gate electrode of said transistor is pulsed with a clocked voltage signal.
Claim 11
Dependent Claim
23 words
The sense circuit of claim 9 wherein said first and second differential voltage level sensing circuits each comprise a cross-coupled sense amplifier circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-11 | 1991-07-13 | 1992-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-11 | 1995-07-13 | 1996-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-11 | 1999-07-13 | 2000-01-12 | $7700.00 | Window Closed / Lapsed |