Memory device

Claim 2

A monolithic integrated circuit comprising a plurality of logic devices each comprising an input, a plurality of programmable circuits each comprising a resistor and a diode device and adapted to be programmed in response to application of programming signals, said logic devices normally being adversely affected by the application of programming signals, each of said resistors coupling a selected one of said logic device inputs through a respective, associated diode device to a common reference point, each of said diode devices initially exhibiting a high impedance, means for modifying said logic devices comprising means for applying programming signals to the junctions between selected ones of said resistors and their associated diode devices to cause said last named diode devices to irreversibly exhibit a bidirectional low impedance which establishes the associated reference states at said last names junctions, said resistors being dimensioned to block such adverse programming signal effects on said logic elements by said first means.

Claim 3

The improved memory device of claim 1 wherein each diode device presenting a low impedance from said resistor to said common reference point comprises a path formed by melted and solidified metal of said diode device connections.

Claim 4

The improved memory device of claim 1 or claim 2 wherein said integrated circuit is an integrated injection logic device.

Claim 5

An improved programmable integrated circuit comprising a plurality of programming signal inputs, a plurality of diode devices, a respective one of said diode devices being connected between each of said inputs and a common reference point with the forward direction of diode device current flow arranged to be from said input to said common reference point, a plurality of logic devices each of which is adversely affected by the application of programming signals to such programming signal inputs, said logic devices connected in cascade to provide a serial output, a plurality of resistors, one of said resistors being connected between each of said inputs and each of said logic devices respectively, selected one of said diode devices normally exhibiting a low impedance from their associated resistors to said common reference point, means for programming said series cascaded logic circuits comprising means for irreversibly programming said selected ones of said diode devices to cause said selected diode devices to exhibit a high impedance from their associated resistors to said common reference point in response to such programming signals applied to associated programming signal inputs, said resistors being dimensioned to block such adverse applied programming signal effects on said logic elements.

Claim 6

An improved programmable integrated circuit comprising a plurality of programming signal inputs, a plurality of diode devices, a respective one of said diode devices being connected between each of said inputs and a common reference point with the forward direction of diode device current flow arranged to be from said input to said common reference point, a plurality of logic devices each of which is adversely affected by the application of programming signals to such programming signal inputs, said logic devices connected in cascade to provide a serial output, a plurality of resistors, one of said resistors being connected between each of said inputs and each of said logic devices respectively, selected one of said diode devices normally exhibiting a low impedance from their associated resistors to said common reference point, means for programming said series cascaded logic circuits comprising means for irreversibly programming said selected ones of said diode devices to cause said selected diode devices to exhibit a high impedance from their associated resistors to said common reference point in response to such programming signals applied to associated programming signal inputs, said resistors being dimensioned to block such adverse applied programming signal effects on said logic elements.

Claim 7

The improved memory device of claim 4 wherein each diode device presenting a low impedance from said resistor to said common reference point comprises a path formed by melted and solidified metal of said diode device connections.

Claim 8

The improved device of claim 4 or claim 5 wherein said integrated circuit is an integrated injection logic device.

Claim 9

In combination, an array of logic elements, means for combining said logic elements in a cascaded circuit to provide a serial output, each of said logic elements comprising first and second inputs and an output, programming circuits for programming given ones of said logic elements, each of said programming circuits comprising a programming signal limiter and an associated unidirectional conducting device, each of said unidirectional conducting devices comprising two terminals, means establishing a reference signal state at one terminal of each of said unidirectional conducting devices, means comprising said signal limiters each coupling the other terminal of its associated unidirectional conductive device to said first input of a respective logic element, each of said unidirectional conducting devices initially exhibiting a high impedance, and first means for applying first programming signals to the junctions between selected ones of said signal limiters and associated unidirectional conducting devices of said programming circuits to cause said last named unidirectional conducting devices to irreversibly exhibit a bidirectional low impedance which establishes the associated reference states at said last named junctions, said signal limiters being dimensioned to block adverse programming signal effects on said logic elements by said last named means.

Claim 10

In combination, an array of logic elements, means for combining said logic elements in a cascaded circuit to provide a serial output, each of said logic elements comprising first and second inputs and an output, programming circuits for programming given ones of said logic elements, each of said programming circuits comprising a programming signal limiter and an associated unidirectional conducting device, each of said unidirectional conducting devices comprising two terminals, means establishing a reference signal state at one terminal of each of said unidirectional conducting devices, means comprising said signal limiters each coupling the other terminal of its associated unidirectional conductive device to said first input of a respective logic element, each of said unidirectional conducting devices initially exhibiting a high impedance, and first means for applying first programming signals to the junctions between selected ones of said signal limiters and associated unidirectional conducting devices of said programming circuits to cause said last named unidirectional conducting devices to irreversibly exhibit a bidirectional low impedance which establishes the associated reference states at said last named junctions, said signal limiters being dimensioned to block adverse programming signal effects on said logic elements by said last named means.

Claim 11

An arrangement according to claim 7 further comprising second means for applying second programming signals to the junction between selected other ones of said signal limiters and associated unidirectional conducting devices of said programming circuits to establish the logic state corresponding to that of said second programming signals at said last named junctions, said logic elements responsive to control signals applied to said second inputs for providing said serial output in accordance with the logic states established at the junctions of said programming circuits.

Claim 12

A programmable shift register comprising an array of logic elements, a load circuit, means for combining said logic elements in a cascaded circuit to provide a serial output to said load circuit, each of said logic elements comprising first and second inputs and an output, programming circuits for programming given ones of said logic elements, each of said programming circuits comprising a resistor and an associated two terminal unidirectional conducting device, means establishing a reference signal state at one terminal of each of said unidirectional conducting devices, means comprising said resistors each coupling the other terminal of its associated unidirectional conductive device to said first input of a respective logic element, each of said devices initially exhibiting a high impedance, and first means for applying first programming signals to the junction between selected ones of said resistor and associated unidirectional conducting devices of said programming circuits to cause said last named unidirectional conducting devices to irreversibly exhibit a bidirectional low impedance which establishes said reference states at said last named junctions, said resistors being dimensioned to block adverse programming signal effects on said logic elements by said first means.

Claim 13

A programmable shift register comprising an array of logic elements, a load circuit, means for combining said logic elements in a cascaded circuit to provide a serial output to said load circuit, each of said logic elements comprising first and second inputs and an output, programming circuits for programming given ones of said logic elements, each of said programming circuits comprising a resistor and an associated two terminal unidirectional conducting device, means establishing a reference signal state at one terminal of each of said unidirectional conducting devices, means comprising said resistors each coupling the other terminal of its associated unidirectional conductive device to said first input of a respective logic element, each of said devices initially exhibiting a high impedance, and first means for applying first programming signals to the junction between selected ones of said resistor and associated unidirectional conducting devices of said programming circuits to cause said last named unidirectional conducting devices to irreversibly exhibit a bidirectional low impedance which establishes said reference states at said last named junctions, said resistors being dimensioned to block adverse programming signal effects on said logic elements by said first means.

Claim 14

An arrangement according to claim 7 further comprising second means for applying second programming signals to the junction between selected other ones of said resistors and associated unidirectional conducting devices of said programming circuits to establish the logic state corresponding to that of said second programming signals at said last named junctions, said logic elements responsive to control signals applied to said second inputs for providing a serial output to said load circuit in accordance with the logic states established at the junctions of said programming circuits.

Claim 15

In combination, an array of logic elements, means for combining said logic elements in a cascaded circuit to provide a serial logic output, each of said logic elements comprising first and second inputs and an output, programming circuits for programming given ones of said logic elements, each of said programming circuits comprising a programming signal limiter and a two terminal unidirectional conducting device, means for establishing a desired signal state at one terminal of each of said unidirectional conducting devices, means comprising said signal limiters each coupling the other terminal of its associated unidirectional conductive device to said first input of a respective logic element, each of said devices initially exhibiting a high serial impedance, first means for selectively applying programming signals to the junctions between said signal limiters and associated unidirectional conducting devices of given ones of said programming circuits to cause said unidirectional conducting devices to irreversibly exhibit a bidirectional low signal impedance which establishes the associated desired states at said junctions, said signal limiters being dimensioned to block adverse programming signal effects on said logic elements by said first means, and said logic elements responsive to control signals applied to said second inputs for providing a serial logic output in accordance with the established logic states at said junctions.

Claim 16

In combination, an array of logic elements, means for combining said logic elements in a cascaded circuit to provide a serial logic output, each of said logic elements comprising first and second inputs and an output, programming circuits for programming given ones of said logic elements, each of said programming circuits comprising a programming signal limiter and a two terminal unidirectional conducting device, means for establishing a desired signal state at one terminal of each of said unidirectional conducting devices, means comprising said signal limiters each coupling the other terminal of its associated unidirectional conductive device to said first input of a respective logic element, each of said devices initially exhibiting a high serial impedance, first means for selectively applying programming signals to the junctions between said signal limiters and associated unidirectional conducting devices of given ones of said programming circuits to cause said unidirectional conducting devices to irreversibly exhibit a bidirectional low signal impedance which establishes the associated desired states at said junctions, said signal limiters being dimensioned to block adverse programming signal effects on said logic elements by said first means, and said logic elements responsive to control signals applied to said second inputs for providing a serial logic output in accordance with the established logic states at said junctions.

Claim 17

An arrangement according to claim 11 further comprising second means to selectively apply second logic signals to dynamically establish logic states at given other ones of said programming circuits to establish the logic states corresponding to that of said second logic signals.