Frequency synthesizer

Claim 2

A programmable frequency synthesizer, comprising: means for providing a reference signal; means for adaptively dividing said reference signal to provide a divided signal; voltage controlled oscillator means for providing an output signal in response to a control signal; means for simultaneously frequency modulating said output signal and said divided signal with an information signal to provide, respectively, a modulated output signal and a modulated divided signal, whereby the frequency synthesizer may be modulated down to approximately zero hertz; prescaler means for dividing said modulated output signal to provide a scaled output signal; means for comparing said modulated divided signal and said scaled output signal to provide a phase error signal; means for adaptively filtering said phase error signal to provide said control signal; means for controlling at least said adaptive divider means and said adaptive filtering means; means for serially programming said control means, whereby, the frequency synthesizer may be rapidly reprogrammed.

Claim 3

The programmable frequency synthesizer of claim 1, wherein said adaptive dividing means comprises: a first divider operable to divide said reference signal by either 7 or 8 to provide an intermediate signal; a second divider, coupled to the first divider, for dividing said intermediate signal by a predetermined value to provide said divided signal.

Claim 4

The programmable frequency synthesizer of claim 1, wherein said comparing means comprises a sample and hold phase comparator.

Claim 5

The programmable frequency synthesizer of claim 1, wherein said adaptive filter means operates in a first mode to filter said error signal, and operates in a second mode to bypass said filter.

Claim 6

The programmable frequency synthesizer of claim 4, wherein said adaptive filter comprises a transmit filter.

Claim 7

The programmable frequency synthesizer of claim 4, wherein said adaptive filter comprises a receive filter.

Claim 8

The programmable frequency synthesizer of claim 1, which further includes means for generating a negative voltage.

Claim 9

The programmable frequency synthesizer of claim 7, which includes means for dividing said negative voltage to provide a plurality of negative voltages, and means for coupling a selected one of said plurality of negative voltage to said voltage controlled oscillator.

Claim 10

A programmable frequency synthesizer, comprising: means for providing a reference signal; means for predeterminedly dividing said reference signal to provide a first divided signal; means for adaptively dividing said first divided signal to provide a second divided signal; voltage controlled oscillator means for providing an output signal in response to a control signal; means for simultaneously frequency modulating said output signal and said second divided signal with an information signal to provide, respectively, a modulated output signal and a modulated divided signal, whereby the frequency synthesizer may be modulated down to approximately zero hertz; prescaler means for dividing said modulated output signal to provide a scaled output signal; means for comparing said modulated divided signal and said scaled output signal to provide a phase error signal; means for adaptively filtering said phase error signal to provide said control signal, whereby said adaptive filtering means operates in a first mode to filter said phase error signal and is temporarily shorted in a second mode to facilitate rapid synthesizer reprogramming; means for controlling at least said adaptive divider means and said adaptive filtering means; means for serially programming said control means, whereby, the frequency synthesizer may be rapidly reprogrammed.

Claim 11

A programmable frequency synthesizer, comprising: means for providing a reference signal; means for predeterminedly dividing said reference signal to provide a first divided signal; means for adaptively dividing said first divided signal to provide a second divided signal; voltage controlled oscillator means for providing an output signal in response to a control signal; means for simultaneously frequency modulating said output signal and said second divided signal with an information signal to provide, respectively, a modulated output signal and a modulated divided signal, whereby the frequency synthesizer may be modulated down to approximately zero hertz; prescaler means for dividing said modulated output signal to provide a scaled output signal; means for comparing said modulated divided signal and said scaled output signal to provide a phase error signal; means for adaptively filtering said phase error signal to provide said control signal, whereby said adaptive filtering means operates in a first mode to filter said phase error signal and is temporarily shorted in a second mode to facilitate rapid synthesizer reprogramming; means for controlling at least said adaptive divider means and said adaptive filtering means; means for serially programming said control means, whereby, the frequency synthesizer may be rapidly reprogrammed.

Claim 12

The programmable frequency synthesizer of claim 9, wherein said comparing means comprises a sample and hold phase comparator.

Claim 13

The programmable frequency synthesizer of claim 9, wherein said adaptive filter comprises a transmit filter.

Claim 14

The programmable frequency synthesizer of claim 9, wherein said adaptive filter comprises a receive filter.

Claim 15

The programmable frequency synthesizer of claim 9, which further includes means for generating a negative voltage.

Claim 16

The programmable frequency synthesizer of claim 13, which includes means for dividing said negative voltage to provide a plurality of negative voltages, and means for coupling a selected one of said plurality of negative voltage to said voltage controlled oscillator.

Claim 17

A serial programming protocol, for programming a programmable frequency synthesizer, comprising the steps of: (a) asserting a select signal; (b) synchronously transmitting 38 data bits consisting of: (i) 8 bits of reference divider data; (ii) a portable/mobile select bit; (iii) a buffer limiter select bit; (iv) a phase modulator activation bit; (v) 19 bits of loop divider data; (vi) a transmit/receive select bit; (vii) 2 bits of multiplexer data; (viii) 3 auxiliary output data bits; (ix) a battery saver mode enable bit; (x) a fast-lock adapt mode enable bit; (c) removing said select signal of step (a).

Claim 18

A serial programming protocol, for programming a programmable frequency synthesizer, comprising the steps of: (a) asserting a select signal; (b) synchronously transmitting 38 data bits consisting of: (i) 8 bits of reference divider data; (ii) a portable/mobile select bit; (iii) a buffer limiter select bit; (iv) a phase modulator activation bit; (v) 19 bits of loop divider data; (vi) a transmit/receive select bit; (vii) 2 bits of multiplexer data; (viii) 3 auxiliary output data bits; (ix) a battery saver mode enable bit; (x) a fast-lock adapt mode enable bit; (c) removing said select signal of step (a).

Claim 19

In a frequency synthesizer having a reference element and a first divider for providing a reference signal (FR) and second divider for dividing an output signal to provide a loop signal (FV), the FR and FV signals being compared in a phase comparator to provide an error signal to an adaptable buffer and filter, and said frequency synthesizer being programmable during a time period determined by an asserted select signal, a method for rapidly acquiring another frequency comprising the steps of: (a) asserting the select signal; (b) providing at least data for programming a first and second divider and an adapt command signal; (c) programming said first divider upon the removal of the select signal of step (a); (d) asserting said adapt command signal upon the occurrence of the first rising edge of the FR signal; (e) programming said second divider upon the occurrence of the first rising edge of the FV signal; (f) adapting the buffer in response to step (d); (g) shorting the filter in response to step (d); (h) removing the adapt command signal after a predetermined time interval; (i) returning the adaptive buffer to its original state; (j) returning the adaptive filter to its original state.

Claim 20

In a frequency synthesizer having a reference element and a first divider for providing a reference signal (FR) and second divider for dividing an output signal to provide a loop signal (FV), the FR and FV signals being compared in a phase comparator to provide an error signal to an adaptable buffer and filter, and said frequency synthesizer being programmable during a time period determined by an asserted select signal, a method for rapidly acquiring another frequency comprising the steps of: (a) asserting the select signal; (b) providing at least data for programming a first and second divider and an adapt command signal; (c) programming said first divider upon the removal of the select signal of step (a); (d) asserting said adapt command signal upon the occurrence of the first rising edge of the FR signal; (e) programming said second divider upon the occurrence of the first rising edge of the FV signal; (f) adapting the buffer in response to step (d); (g) shorting the filter in response to step (d); (h) removing the adapt command signal after a predetermined time interval; (i) returning the adaptive buffer to its original state; (j) returning the adaptive filter to its original state.