Patent US4714684A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4714684A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming single crystal layer on dielectric layer by controlled rapid heating

Assignee: TODORIKI ITARU DIRECTOR GENERAL AGENCY OF INDUSTRIAL SCIENCE AND TECHNOLOGY
•
Filing: 1986-03-26
•
Granted: 1987-12-22
•
Expires: 2006-03-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract In a method of manufacturing a semiconductor device of a three-dimensional structure having a semiconductor substrate and another single crystal semiconductor layer formed thereon, the another single crystal semiconductor layer is prepared by melting a vapor-deposited amorphous or polycrystalline semiconductor layer by the energy of laser beams then solidifying and converting the layer into single crystals. For initiating the melting at selected regions of the layer, the layer is formed at the surface thereof with a silicon nitride film of a uniform thickness and a silicon nitride film with a thickness at the region corresponding to the selected region different from that of the remaining region. The region thicker or thinner than other region reflects the laser energy at different reflectivity thereby to provide a desired temperature distribution.

Inventors

  • 👤 Kazuyuki Sugahara
  • 👤 Tadashi Nishimura
  • 👤 Shigeru Kusunoki
  • 👤 Yasuo Inoue

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 13:34
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/38; H10P14/3802; H10P14/3808; H10P14/3814; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/32; H10P14/3202; H10P14/3238; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/382; Y; Y10; Y10S; Y10S117/00; Y10S117/903; Y10S117/904; Y10S148/00; Y10S148/093

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 115 words
A method of manufacturing a semiconductor device comprising: forming a first dielectric layer on a semiconductor substrate, forming an amorphous or polycrystalline semiconductor layer on said first dielectric layer, forming a second dielectric layer of substantially uniform thickness on said semiconductor layer, forming a third dielectric layer on said second dielectric layer, said third dielectric layer being flat on its lower surface but having a plurality of parallel grooves in its upper surface to form regions at the bottom of said grooves having a lesser thickness than the thickness of the remaining regions thereof, and melting and recrystallizing said semiconductor layer by the irradiation of laser beams thereby converting said semiconductor layer into single crystals.
Claim 2
Independent Claim 115 words
A method of manufacturing a semiconductor device comprising: forming a first dielectric layer on a semiconductor substrate, forming an amorphous or polycrystalline semiconductor layer on said first dielectric layer, forming a second dielectric layer of substantially uniform thickness on said semiconductor layer, forming a third dielectric layer on said second dielectric layer, said third dielectric layer being flat on its lower surface but having a plurality of parallel grooves in its upper surface to form regions at the bottom of said grooves having a lesser thickness than the thickness of the remaining regions thereof, and melting and recrystallizing said semiconductor layer by the irradiation of laser beams thereby converting said semiconductor layer into single crystals.
Claim 3
Dependent Claim 39 words
A method of manufacturing a semiconductor device as defined in claim 1, comprising the semiconductor substrate composed of silicon, the first and second dielectric layers both composed of silicon oxide and the third dielectric layer composed of silicon nitride.
Claim 4
Dependent Claim 56 words
A method of manufacturing a semiconductor device as defined in claim 2, wherein the thickness of the second dielectric layer is within a range from 0.04 to 0.07 μm and the third dielectric layer comprises a region of a thickness from 0.01 to 0.03 μm and a region of a thickness from 0.05 to 0.1 μm.
Claim 5
Dependent Claim 56 words
A method of manufacturing a semiconductor device as defined in claim 2, wherein the thickness of the second dielectric layer is within a range from 0.07 to 0.1 μm and the third dielectric layer comprises a region of a thickness from 0 to 0.03 μm and a region of a thickness from 0.04 to 0.1 μm.
Claim 6
Dependent Claim 58 words
A method of manufacturing a semiconductor device as defined in claim 2, wherein the step of forming the third dielectric layer comprises; forming a silicon nitride film of a desired thickness on the second dielectric layer; removing the thus formed silicon nitride layer from desired regions and then forming another silicon nitride film on said silicon nitride film.
Claim 7
Dependent Claim 29 words
A method of manufacturing a semiconductor device as defined in claim 5, wherein said silicon nitride film and said another silicon nitride film are formed by the CVD process.
Claim 8
Dependent Claim 31 words
A method of manufacturing a semiconductor device as defined in claim 5, wherein the step of removing a portion of the silicon nitride film is carried out by a photo-etching process.

References Cited (Backward Citations)

US4431459A Cited
US4523962A Cited
US4514895A Cited
US4543133A Cited
US4545823A Cited
US4619038A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-12-21 1991-06-22 1991-12-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-12-21 1995-06-22 1995-12-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-12-21 1999-06-22 1999-12-22 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag